由於半導體製程技術在過去30年的快速發展，許多相關應用之現代科技得以成功導入市場，半導體業也因此被視為科技相關產業中的龍頭，而因良率（Yield）可說是反應此一關鍵產業中整體技術與企業獲利高低之綜合代表，故在諸多衡量指標中其重要性自不言而喻。簡單的說，良率可定義成產出之良品佔所有投入生產總數的百分比；而良率管理（Yield Management）乃是指針對從整個半導體製造過程中產生龐大資料所作之整合分析、良率改善與預測（Yield Prediction）等相關活動之總稱。這其中，由於在許多方面如生產投料、交貨排程以及工程問題界定釐清等方面皆須仰賴一有效的預測模式，是以良率預測已漸漸成為半導體產業中重要之議題。

　　如上之理由，本論文嘗試提出一有效且簡單之良率預測模式：即以晶圓允收測試（Wafer Acceptance Test）資料為基礎，藉由類神經倒傳遞網路（Artificial Neural Back-Propagation Network）所具有學習、容錯與平行運算等優點來發展出預測晶圓測試（Wafer Test）良率的方法。而為了有效控制神經網路建構的複雜度，本研究將分別應用主成分分析（Principal Component Analysis）與逐步選取變數（Stepwise Variable Selection)二方法來達到降低輸入變數維度之目的；另也將以傳統迴歸分析方法與以上兩組結果分別作不同模式結果之比較，以驗證類神經倒傳遞網路所建構之良率預測模式準確度。

　　而經由本研究所蒐集之資料實際驗證結果顯示，以晶圓允收測試資料結合逐步選取變數與類神經倒傳遞網路的模式，確實可作為一有效的預測晶圓測試良率之方法。

　　Thanks to tremendous advance of semiconductor technology in the last 30 years, several modern technological applications have been introduced to the world successfully. Among the performance indexes for this key industry, yield is regarded as the most important one. As a simple and clear definition , semiconductor yield means the ratio of functional chips shipped from the total number of chips manufactured ; yield management is the activity to integrate a huge and various sources of data generated from the whole manufacturing processes for the purpose of rapid yield learning and prediction. Yield prediction has become a crucial issue, as many aspects of semiconductor operation rely on this ability, like forecasting the time-to-market for volume production; determining the cost of a new chip before fabrication; estimating the number of wafer starts required; identifying and monitoring when a manufacture process is not performing as expected and showing which defect source that results in most yield loss..etc. .

　　For above reasons, this thesis attempts to propose a fast and workable solution for wafer test yield prediction by using WAT (Wafer Acceptance Test) data based on Artificial Neural Back-Propagation Network (BPN) properties of fault-tolerance,learning and parallel processing. To reduce the number of network input variables, two kinds of approaches were adopted:one was PCA (Principal Component Analysis) that expresses the original data information by less of new variables (Principal Component) to achieve the variable dimension reduction purpose; another was by stepwise variable selection method to extraction key variables from all ones. In addition, the two sets of data were also applied to regression analysis for comparisom with BPN model.

　　A real case was presented to demonstrate the methodology and the result revealed that by stepwise variable selection of BPN can provide an acceptable accurance for wafer test yield prediction.

中文文獻部分
1. 財團法人交大思源基金會網頁 http://www.spring.org.tw/plan/a86/case/。

2. 國立清華大學化學系網頁http://www.che.nthu.edu.tw/introduce。

3. 莊達人，民國89年，「VLSI 製造技術」，高立圖書有限公司，台灣。

4. 許志瑋，民國92年，「整合缺陷點數與群聚指標之積體電路良率模式」，國立交通大學工業工程研究所，碩士論文。

5. 許哲強，民國91年，「台灣區域電力負載預測分析系統之建立與應用研究」，國立成功大學資源工程研究所，博士論文。

6. 陳順宇，民國87年，「多變量分析」，華泰書局，台灣。

7. 黃俊英，民國80年，「多變量分析」，中國經濟企業研究所，台灣。

8. 黃峰蕙、施勵行、林秉山，民國86年，「生產與作業管理」，三民書局，台灣。

9. 葉怡成，民國89年，「類神經網路模式應用與實作」，儒林圖書公司，台灣。

10. 盧靜怡，民國90年，「企業經營績效排名之預測－灰色關聯分析與類神經網路之應用」，國立台灣科技大學資訊管理系，碩士
論文。

西文文獻部分
11. Badiru, A.B. and Sieger, D.B., 1998, “Neural network as a simulation metamodel in economic analysis of risky projects”. European Journal of Operation Research, Vol. 105, p.130-142.

12. Box, G.E.P., Hunter, W.G. and Hunter, J.S., 1978, “Statistics for Experimenters. An
Introduction to Design, Data Analysis, and Model Building”, Wiley, Inc., New York.

13. Chaveesuk, R. and Smith, A. E., 1999, “A neural network metamodel approach to capital investment decision analysis”. IEEE Neural Networks International Joint Conference , 3844-3849.

14. Cunningham, J. A., 1990, ”The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing”, IEEE Transactions On Semiconductor Manufacturing, Vol. 3, p.60-
71.

15. Diebold, A.C., 2001, ”Handbook of Silicon Semiconductor Metrology”, Marcel Dekker, Inc., New York.

16. Freeman, J. A. and Skapura, D. M.,1992, “Neural Networks Algorithms, Applications , and Programming Techniques”, Addison-Wesley Publishing Company, New York.

17. Kaiser, H. F. ,1960, “The application of electronic computers to factor analysis”, Education Psychological Measuring , Vol. 20 , p141-151.

18. Mirza, A. I., Donoghue, G.O., Drake, A.W. and Graves, S.C., 1995, “ Spatial Yield Modeling for Semiconductor Wafers”, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, p. 276-281.

19. Murphy, B.T., 1964, “Cost-Size Optima of Monolithic Integrated Circuits”, IEEE Proc. , Vol. 52,no. 12, p. 1537-1545.

20. Rumelhart, D.E., Hintion,G. E. and Willians, R.J.,1986, “Learning Representations by Back-Propagating errors,” Nature, Vol. 323, p.533-536.

21. Seeds, R. B., 1967a, “Yield and Cost Analysis of Bipolar LSI”, IEEE International Electron Meeting, p.12, Oct. , Washington, D.C..

22. Seeds, R.B., 1967b, “Yield, Economic, and Logistic Models for Complex Digital Arrays”, IEEE International Convention Record, Vol. 56, p. 61-66.

23. Stapper, C. H., 1973, ”Defect Density Distribution for LSI Yield Calculations ”, IEEE Transactions on Electron Devices, Vol. ED-20, p. 655-657.

24. Stapper, C. H., Armstrong, F. M. and Saji, K., 1983, “Integrated Circuit Yield Statistics”, IEEE Proc. , Vol. 71, p. 453-470.

25. Stapper, C. H.,1985, “The Effects of Wafer to Wafer Density Variations on Integrated Circuit Defect and Fault Density”, IBM Journal of Research development, Vol.
29, p. 87-97.

26. Stapper, C.H. and Rosner, R.J.,1995, ”
Integrated Circuit Yield Management and Yield Analysis:Development and Implementation”, IEEE Trans. on Semiconductor Manufacturing, Vol. 8, p. 95-102.

27. Stapper, C.H., 1973, “Defect Density Distribution for LSI Yield Calculations”, IEEE Trans. Electron Devices, Vol. 20, p. 655-657.

28. Stapper, C.H., 1976, “LSI Yield Modeling and Process Monitoring”, IBM J. Res. Dev., Vol. 20, p. 228-234.

29. Stapper, C.H., Armstrong, F.M., and Saji, K., 1983, “Integrated Circuit Yield Statistics”, IEEE Proc. , Vol. 71, no. 4, p. 453-470.

30. Vellido, A., Lisboa, P. J.G. and Vaughan, J., 1999, “Neural Networks in Business: A Survey of Applications ”, Expert Systems with Applications, Vol. 17, p.51-70.

31. Walczak S., Cerpa N., 1999, “ Heuristic Principles for the Design of Artificial Neural Networks”, Information and Software Technology, Vol. 41, p. 107-117.

32. Williams, R. J. and Zipser, D., 1989, “A learning algorithm for continually running fully recurrent neural networks”, Neural Computation, Vol. 1, p. 270-280.