現今電子封裝產業利用覆晶封裝技術提高電子元件中積體電路的密度，以滿足產品輕薄化的需求，其中底填膠作為黏合晶片與基板的廣泛使用。底填膠受熱應力等因素所產生的裂紋會導致產品後續有脫層等失效，為電子元件關鍵的失效原因之一。本研究將以底填膠為目標材料，在線黏彈性力學的理論基礎上，對其單材料及界面的破壞力學參數進行分析。
本研究針對底填膠的黏彈特性與破壞力學分析可分為三個主題：黏彈本構模型之建立、三點彎矩破壞韌性量測、黏彈性破壞力學參數分析。透過鬆弛實驗，量測底填膠在不同溫度下的鬆弛模數曲線，建立其黏彈主曲線及溫度平移因子函數。破壞韌性量測則利用三點彎矩實驗對底填膠試片施加模式一負載，量測得底填膠的模式一臨界應力強度因子，並考慮環境溫度、熱固化條件及高溫老化對材料破壞韌性的影響。同時利用有限元素搭配虛擬裂紋閉合法，針對黏彈材料的破壞力學參數進行模擬，結果發現在應變能釋放率的計算上與理論解相同，而應力強度因子則會有黏彈反應過程中準彈性計算的誤差。藉由雙懸臂樑實驗的模擬，可發現其彈破壞力學參數與黏彈材料特性有著相似的趨勢，配合量測所得之黏彈特性，可有根據地評估底填膠與矽晶界面裂紋的成長趨勢。

Underfill has been widely used in flip-chip (FC) packaging to protect the bump interconnect. Cracks in underfill or on its interfaces caused by thermal stress is one of the key failure modes in FC packages. This study investigates the viscoelastic fracture responses of underfill and the Si-underfill interface. By using tensile relaxation tests, the relaxation modulus of the underfill at various temperatures were measured, and the viscoelastic mastercurve and the corresponding temperature shift functions were established. A three-point bending fracture test was conducted to measure the Mode-I critical stress intensity factor of the underfill, and the impact of ambient temperature, curing condition, and thermal aging on the fracture toughness were investigated. Finite element simulation in combination with virtual crack closure integral (VCCI) was applied to calculate the fracture mechanics parameters of the viscoelastic materials. It was shown that the strain energy release rate obtained from the quasi-elastic procedure is the same as analytical solution; while the numerical solution of the stress intensity factor overestimated the variation in the transient viscoelastic regime. Through the simulation of the double cantilever beam (DCB) experiment, it can be found that the time-dependent fracture mechanics parameters follow similar trend as the viscoelastic response of the material.

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