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研究生： 陳世峻
Chen, Shih-Chun
論文名稱： 應用於捲積計算的低錯誤固定長度乘法器的設計
Design of Low-Error Fixed-Width Multiplier for Convolution Computations
指導教授： 郭耀煌
Kuo, Yaw-Huang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 62
中文關鍵詞： 固定長度乘法器 、改進型布斯演算法 、近似進位
外文關鍵詞： approximate carry, fixed-width multipliers, modified Booth algorithm
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    • 　　在本篇論文中，我們提出修改Modified Booth為主的固定長度乘法器，根據乘數與被乘數的大小來補償最後乘積的誤差值，以達到較小的誤差和較小的硬體面積。相對於固定長度乘法器，一般的乘法器需要較多的面積及執行時間來完成一個乘法運算，但其精確度卻是絕對零誤差。然而，對於數位訊號處理捲積應用中，運算後的乘積通常不需要低位元部分，為了降低成本及速度的降低，固定長度乘法器的存在是必要的，但其存在的運算誤差及面積大小將是設計的重點，亦是本篇論文的重點。

    　　一個N×N位元(N為偶數)的固定長度乘法運算中，單純的只取前(N/2)×(N/2)位元作乘法運算，將會產生最大的誤差。為了縮減誤差，將根據乘數與被乘數的大小，預測後面(N/2)×(N/2)個位元的進位值。被移除的後面(N/2)×(N/2)個位元，可以分成二部分: LPmajor 與 LPminor。本論文即為預測後面(N/2)×(N/2)個位元的進位值。最新文獻採用卡諾圖來產生S_LPminor的近似值。然而，當輸入的乘數與被乘數很大時，卡諾圖會變的極大，所以此方法並不適用於大bits數的乘數。故本論文提出另一種方法，根據乘數的大小對乘數做分群，不同的群組便有不同的S_LPminor的估計值。經由模擬以及實驗結果，此論文所提出的方法與最新的文獻相較，MSE最多減少了1.1832，而面積也比modified Booth乘法器少了約15%。

    　The modified Booth fixed-width multiplier receives n-bit input and produces n-bit output. This thesis proposes an error compensation method for a fixed-width multiplier that uses modified Booth algorithm. The truncated part is divided into 2 parts, LPmajor and LPminor. For the reason that LPmajor has dominant effect on the sum of retained cells, S_MP, the sum of LPmajor is computed exactly. The sum of LPminor is computed approximately since it has little contribution on S_MP. Using Karnaugh-map to generate the compensation bias is the first proposed method in this thesis, then another improvement is proposed since it’s time-consuming to draw the K-map from a multiplication of large numbers. The multiplier input values are first classified into several groups and each group is associated with a different compensation bias, which is computed directly from Booth encoder outputs rather than multiplier coefficients. By simulations, the proposed design performs about 2 dB higher PSNR than the existing method. That is, the MSE is reduced up to 1.1832 compared with the state-of-art designs. It saves up to 15% area compared with modified Booth multiplier without truncating any cell.

    應用於捲積計算的低錯誤固定長度乘法器 ii Abstract v 誌謝 vi Table of Contents vii List of Tables ix List of Figures xi Chapter 1 Introduction 1 1.1 Motivation 1 Chapter 2 Background 3 2.1 Basic Concepts of Multiplication 3 2.2 Kinds of Multipliers 4 2.2.1 Iterative Structure Multipliers 4 2.2.2 Array Structure Multipliers 6 2.2.3 Truncated Array Multipliers 7 2.2.4 Fixed-Width Multipliers 8 2.3 Booth’s Algorithm 11 2.4 Modified Booth’s Algorithm 12 2.5 Fixed-Width Modified Booth Multipliers 14 Chapter 3 Design Based on Input Classifications 19 3.1 Compensation Value Estimation Using Karnaugh Map 20 3.2 Input Classifications 25 3.2.1 Classifying into Two Groups 26 3.2.2 Classifying into Four Groups 35 3.2.3 Classifying into Eight Groups 41 3.2.4 Selecting the number of Groups 49 3.3 Multiplier Architecture Based on 4-Group Classificaiton 51 Chapter 4 Simulation and Implementation 53 4.1 Implementation by using Verilog HDL 53 4.2 Comparisons of Area 53 4.3 Applications 55 Chapter 5 Conclusion and Future Work 62 References 63

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