本論文提出一個應用於無線區域網路 802.11ax 之基於砷化鎵異質接面雙載子電晶體的堆疊式架構功率放大器。為了能達到 Wi-Fi 6E 之規格需求，本研究設計了一個三級串接架構的功率放大器。由於對於功率放大器而言輸出功率、效率以及增益之間的權衡關係相當緊張，因此對於電晶體的尺寸及偏壓條件的挑選便成為設計的第一步。其次，為了能夠更加提升電路在高功率操作下的線性度表現，本研究設計了一個能夠補償直流偏壓衰減的自適應偏壓電路。最後，透過負載牽引模擬找出最適當的負載值，並透過級間匹配的適當設計來確保在不產生級間震盪的情況下能夠同時擁有良好的增益與輸出功率。然而，三級的串接架構將消耗非常大的面積在於匹配電路的設計上，而為了在縮小面積的同時能夠繼續保持高增益及輸出功率，本研究又提出了堆疊式的架構。堆疊式架構有別於傳統的疊接架構，其差別在於在電晶體的基極多接上一個對地電容，使得其與電晶體本身的寄生電容產生電壓分壓的效果，讓電晶體的基極不再是訊號接地的情形，進一步提升電晶體集極的擺幅，來提升電路的輸出功率。本研究使用穩懋以及宏捷科的砷化鎵異質接面雙載子電晶體製程實現此電路。此電路最後的量測結果在集極電源電壓為 5 伏特的情況下在中心頻率為 6.525 千兆赫茲的頻帶裡達到增益為 27.2 dB，，和輸輸出功率為 25.4 dBm，，值值功率附加效率為 37.8 %，面積為 1.6 平方毫米，以及功率密度為 216.7 毫瓦/平方毫米。

This thesis presents a stacked architecture power amplifier (PA) based on Gallium Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) technology, designed for application in wireless local area network (WLAN) 802.11ax. To meet the specifications of Wi-Fi 6E, a three-stage cascade architecture PA was designed. The first step in the design process involves selecting the transistor sizes and bias conditions, given the critical tradeoffs among output power, efficiency, and gain for PAs. Next, to enhance the linearity performance of the circuit under high-power operation, an adaptive bias circuit was designed to compensate for DC bias degradation. Finally, an optimal load value was determined through load-pull simulations, and appropriate interstage matching design was implemented to ensure good gain and output power without causing inter-stage oscillation. However, the three-stage cascade architecture consumes significant area due to the matching circuit design. A stacked architecture was proposed to reduce the area while maintaining high gain and output power. The stacked architecture differs from traditional cascade structures by adding a capacitor to the ground at the transistor's base. This creates a voltage divider effect with the transistor's parasitic capacitance, preventing the base from being at AC ground and enhancing the collector swing to improve the circuit's output power. The circuit was implemented using the GaAs HBT processes from WIN Semiconductors and AWSC. The final measurement results show that, with a collector supply voltage of 5 V, the PA achieves a gain of 27.2 dB, a saturated output power of 25.4 dBm, a peak PAE of 37.8%, an area of 1.6 mm², and a power density of 216.7 mW/mm² at a center frequency of 6.525 GHz.

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