為開發新穎通道層材料，本論文利用共濺鍍沉積技術，製備氧化矽鋯之介電層與開發鋯摻雜氧化銦鎵鋅(Zr-doped IGZO)之通道層，以改善介電層/通道層之界面缺陷，並探究其於薄膜電晶體電特性與可靠度之改善。
本研究分為兩大部分，第一部分為接續本實驗室先前開發氧化矽鋯閘極介電層，藉由摻入適當含量之矽元素於二氧化鋯介電層中，改善二氧化鋯介電層之薄膜品質且有效降低與氧化銦鎵鋅通道層之界面缺陷密度。本論文亦沉積二氧化矽與二氧化鋯之堆疊結構作為對照，以分析比較其界面於元件特性與可靠度之影響；第二部分為利用共濺鍍技術以二氧化鋯與二氧化矽靶材開發鋯摻雜氧化銦鎵鋅薄膜，並調變各項參數於鋯摻雜氧化銦鎵鋅通道層探究對元件特性之影響，除藉由調變沉積功率以改變通道層材料成份組成之比例與厚度，進行其薄膜分析、元件電特性與可靠度之研究外，亦探討經由熱退火製程的Zr-doped IGZO通道層對於材料分析、元件電特性與可靠度之影響。
於本論文第一部分，首先討論二氧化鋯與二氧化矽以堆疊式結構或共濺鍍技術製備介電層，及其應用於氧化銦鎵鋅薄膜電晶體時，觀察界面的不同造成元件特性與可靠度之差異。實驗結果指出，經由摻入適量的Si元素以氧化矽鋯有較佳的界面品質及較少的界面缺陷，可有效提升元件之特性。本研究進一步分析此元件之可靠度，於偏壓應力方面，施予±4 V閘極偏壓，其臨界電壓偏移量分別從ZrO2的1.11 V與-0.96 V降低至Zr0.85Si0.15O2的0.77與-0.57 V；於熱穩定方面，設定環境溫度從初始溫度298K升溫至378 K，其臨界電壓偏移量從-0.98 V降至-0.45 V，顯示元件可靠度亦獲得有效改善。
於本論文第二部分，利用Zr元素與氧鍵結較強且電負度較小之特點，藉由共濺鍍技術摻入於IGZO通道層以抑制氧空缺的產生，改善傳統氧化銦鎵鋅薄膜高缺陷密度之通病，提升氧化銦鎵鋅通道層之薄膜品質。由於Zr元素易與氧形成鍵結，使氧原子不易游離，進而捕捉氧氣以修復薄膜原本存留的氧空缺。另一方面，摻入Zr元素使得IGZO薄膜之能隙增加與施體能階減少，因而降低其漏電流。此外，進一步藉由熱退火處理以修補及活化鋯摻雜氧化銦鎵鋅薄膜之品質，而達成其元件特性與可靠度之優化。
依據實驗結果顯示，摻入適量Zr元素之IGZO通道層，確實可改善薄膜的品質亦減少介電層/通道層界面之缺陷密度，更有助於降低氧空缺之含量。本研究發現經300 oC氮氣環境下退火的Zr(2.0 %)-IGZO TFT，展現最佳元件之特性與可靠度，其載子遷移率為18.3 cm2/V∙s、次臨界擺幅為96 mV/dec、元件電流開關比為1.59×108、臨界電壓為0.56 V與界面缺陷密度為1.09×10^12 cm-2eV-1；於正負偏壓應力測試實驗部分，臨界電壓偏移量分別為0.22 V和-0.15 V；於熱穩定度部分，其臨界電壓偏移量為-0.13 V。綜合以上實驗結果符合本論文之研究目的。
本實驗以共濺鍍技術製備鋯摻雜氧化銦鎵鋅通道層之薄膜電晶體，成功改善其界面品質、閘極控制能力、元件特性與可靠度，故有助於未來顯示技術之應用以及電子產品性能之提升。

The performance of zirconium doped indium gallium zinc oxide thin-film transistors (Zr-IGZO TFTs) with zirconium silicon oxide (Zr0.85Si0.15O2) as gate dielectrics using a RF co-sputtering technique is investigated. Through incorporation of zirconium in channel to reduce the oxygen vacancies formation which have been confirmed by X-ray photoelectron spectroscopy (XPS) analysis. It is exhibited that the stability of Zr-IGZO TFTs are better than IGZO TFTs under the positive and negative gate bias stresses (PGBS and NGBS). Experimental results reveal that Zr-IGZO channel was deposited at a power ratio of IGZO:ZrO2=80 W:50 W by post deposition annealing (PDA) in N2 shows the best device performance such as the on/off current ratio of 1.59×10^8, the subthreshold swing of 96 mV/dec, and the threshold voltage shift after 1000 sec positive/negative gate bias stress of 0.22 V/-0.13 V, respectively.

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