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研究生: 王建順
Wang, Chien-Shun
論文名稱: 一個新穎的利用預先估算最小平方誤差之色彩內插演算法及硬體架構
A Novel Color Interpolation Algorithm and Hardware Architecture by Pre-estimating Minimum Square Error
指導教授: 王駿發
Wang, Jhing-Fa
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系碩士在職專班
Department of Electrical Engineering (on the job class)
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 87
中文關鍵詞: 色彩內插矩陣運算
外文關鍵詞: Color Interpolation, Digital Still Camera, Color Filter Array, Schur algorithm, CFA, Systolic array
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  •   在近年來,數位相機成為非常受歡迎的消費性電子產品。大多數數位相機使用單一電荷藕元件(CCD)及結合彩色濾波器矩陣(CFA)去擷取彩色影像。本論文提出使用在數位相機內的一個新穎的色彩內插演算法,論文中我們介紹利用預先估算最小平方誤差來補插還原彩色濾波器矩陣的彩色影像。為了估算在彩色濾波器矩陣影像中所失去的像素值,鄰近色彩像素的權重值是由矩陣運算所決定出。過程中我們亦採用已使用在多數色彩內插演算法的色彩模型(KR, KB)。實驗結果證明我們所提出的方法可以達到很好的效果。相較於一般的方法,我們的方法可以在數位相機系統中提供高品質的影像和有規則的硬體架構設計。為了達到有效率的硬體實現,我們亦針對硬體部份提出一個modified recursive Schur algorithm,來將我們所提出的內插演算法做硬體實現。

     In recent years, digital still cameras (DSCs) are becoming very popular consumer electronic devices. Most digital still cameras use single Charge-Coupled Device (CCD) with Color Filter Array (CFA) to capture sub-sampled digital color images. In this thesis, a novel color interpolation algorithm for Color Filter Array (CFA) in digital still cameras (DSCs) is presented. This work introduces pre-estimating the minimum square error to address the color interpolation for CFA. In order to estimate the missing pixels in Bayer CFA pattern, the weights of adjacent color pattern pairs are decided by the matrix computation. We adopt the color model (KR, KB) used in many color interpolation algorithms for CFA. The proposed algorithm can achieve better performance shown in the experimental results. Comparing the previous methods, the proposed color interpolation algorithm can provide high quality image in DSCs and regular architecture for VLSI design. For the purpose of the efficient hardware implementation, we propose a modified recursive Schur algorithm for hardware design of the proposed interpolation Algorithm.

    ABSTRACT I 誌 謝 III LIST OF TABLE ……………………………………………………………………VI LIST OF FIGURE ………………………………………………………………….VII CHAPTER 1. INTRODUCTION………………………………………………….1 1.1. BACKGROUND.........................................................................................................1 1.2. SINGLE CCD AND 3CCD.........................................................................................2 1.3. COLOR FILTER ARRAY INTERPOLATION PATTERN....................................................4 1.4. PREVIOUS WORK.....................................................................................................5 1.5. Thesis Organization................................................................................................6 CHAPTER 2. REVIEW OF EXISTING COLOR FILTER ARRAY INTERPOLATION ALGORITHM…………………...………….7 2.1. BILINEAR INTERPOLATION METHOD 7 2.2. EDGE SENSING INTERPOLATION ALGORITHM 10 2.3. SMOOTH HUE TRANSITION INTERPOLATION ALGORITHM 13 2.4. EFFECTIVE COLOR INTERPOLATION ALGORITHM 14 CHAPTER 3. PROPOSED NOVEL COLOR INTERPOLATION ALGORITHM 17 3.1. INTRODUCTION 17 3.2. BASIC DESCRIPTION OF PROPOSED COLOR INTERPOLATION ALGORITHM 18 3.3. BASIC ILLUSTRATION OF PROPOSED COLOR INTERPOLATION ALGORITHM 20 3.3.1 G Channel Interpolation at B Pixel 22 3.3.2 G Channel Interpolation at R Pixel 24 3.3.3 R Channel Interpolation at B Pixel 24 3.3.4 R Channel Interpolation at G Pixel (mode 1) 26 3.3.5 R Channel Interpolation at G Pixel (mode 2) 29 3.3.6 B Channel Interpolation 30 3.4. PERFORMED THE IMPROVEMENT OF PROPOSED COLOR INTERPOLATION ALGORITHM 30 3.4.1 G Channel Interpolation at B Pixel..................................................................31 3.4.2 G Channel Interpolation at R Pixel..................................................................33 3.4.3 R/B Channel Interpolation...............................................................................34 CHAPTER 4. HARDWARE DESIGN OF THE PROPOSED INTERPOLATION ALGORITHM 36 4.1. SOLVING TOEPLITZ SYSTEM (SCHUR ALGORITHM) 36 4.2. THE PROPOSED MODIFIED RECURSIVE SCHUR ALGORITHM FOR HARDWARE DESIGN 39 4.2.1 Modified Recursive Schur algorithm for 3-order matrix..................................39 4.2.2 Modified Recursive Schur algorithm for 5-order matrix..................................43 4.2.3 Hardware Design of the Modified Recursive Schur algorithm.........................50 4.2.4 The flowchart of the proposed Modified Recursive Schur algorithm...............55 4.2.5 Systolic array design.........................................................................................57 4.2.6 Timing Diagram................................................................................................64 4.2.7 Schematic and Simulation Result......................................................................65 CHAPTER 5. EXPERIMENTAL RESULTS 67 5.1. VISUAL COMPARISON............................................................................................67 5.2. PEAK SIGNAL TO NOISE RATIO (PSNR) COMPARISON...........................................80 5.3. COMPLEXITY ANALYSIS........................................................................................82 CHAPTER 6. CONCLUSIONS………………………………………………….85 REFERENCES 86

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