近年來CMOS製程為了跟隨著摩爾定律的演進，尺寸逐漸的萎縮，從2D平面MOSFET到近期的3D鰭式場效應電晶體(FinFET)，都是為了在尺寸微縮下能保持通道控制力下所演進的。如今，FinFET對通道的控制能力已有不足的現象產生，環繞式閘極(Gate-All-Around)結構被提了出來，解決了FinFET沒辦法在尺寸更萎縮的狀況無法控制通道的窘境。
然而GAA結構從一開始的奈米線(Nanowire)到現今的奈米片(Nanosheet)，增加了提堆疊的可能性，因此有了將N型和P型奈米片堆疊在一起的結構，稱這結構為堆疊式互補式電晶體(CFET)，提升了晶片萎縮的可能性，因而成為了下一個CMOS工藝技術發展的候選者。而TSRI根據此結構提出了具有多晶矽通道的無接面式CFET，其製程具有低溫且有著容易做三維堆疊的特性，因此適用於積層型三維製程整合電路(Monolithic 3D Integrated Circuit)。
在此論文中，我們根據TSRI發表的CFET製程工藝，利用TCAD的Sprocess模擬，模擬出相近於TSRI所發表的CFET模型，並將其作電性分析以及射頻分析，並且對各種製程參數做獨自的分析，分析其優缺點，最後去優化出在不更改製程順序狀況下最好的CFET模型，並與原本TSRI提供的模型的表現作比較。最後我們提出了更改一小部分的製程步驟，研究出另一種型態的CFET並與原本做比較，研究其新製程所帶來的優勢。
在更改製程參數以及更改製程步驟的情況下，CFET的RF特性比起原本模型有大幅的優化。在此論文中會循序漸進的介紹優化的過程以及製程參數的選用，且做出優化的CFET模型。以供TSRI有更好的製程方向。

In recent years, CMOS processes the evolution of Moore's Law. The device's size shrinks gradually, and device structure evolves from 2D planar MOSFETs to the current 3D fin-type field-effect transistors (FinFETs), which are developed to shrink in size while maintaining channel control. Today, as FinFETs have insufficient control over the channel. Gate-All-Around (GAA) structure was proposed to solve the dilemma that FinFETs cannot control the channel with the shrinking size.
However, the GAA structure from the beginning of the Nanowire (Nanowire) to the current Nanosheet (Nanosheet), increasing the possibility of stacking, so there are N-type and P-type nanosheet stacking structure, called this structure can stackable complementary transistors (CFET), enhance the probability of wafer shrinkage, and therefore become the following CMOS process technology development candidates. TSRI has proposed a junctionless CFET with polysilicon channels based on this structure, which has low temperature and is suitable for Monolithic 3D Integrated Circuit.
In this paper, we use TCAD's Sprocess simulation to simulate a CFET model similar to the one published by TSRI, and analyze its electrical properties as well as RF analysis, and do independent research of each process parameter, analyze its strengths and weaknesses, and finally optimize the best CFET model without changing the process flow situation. And compared with the performance of the original model provided by TSRI. Finally, we propose to change a small part of the process steps to investigate another type of CFET compared with the original to study the advantages of the new process.
In the case of changing the process parameters and the process steps, the RF characteristics of the CFET are significantly optimized compared to the original model. This paper will introduce the optimization process and the selection of process parameters step by step and make the optimized CFET model to provide TSRI with better process direction.

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