在過去幾十年中，半導體產業持續遵循摩爾定律，逐步提高電路密度，然而，隨著製程微縮(more Moore)面臨越來越大的挑戰，產業界開始探索more than Moore的發展路徑，以實現異質整合和三維堆疊技術。在這背景下，矽穿孔(Through Silicon Via, TSV)技術成為晶片間垂直連接其關鍵技術，透過導孔內的金屬連接，矽穿孔技術不僅能夠縮小尺寸，還能實現3D堆疊及異質整合。儘管TSV技術具有多項優勢，但在高溫製程中，材料間膨脹係數的不匹配會引發熱應力，這是TSV技術所面臨的一大挑戰。此熱應力可能導致TSV結構出現銅凸或脫層等問題，進而影響元件的性能和可靠性。此外，已有研究顯示，熱應力會引起矽晶格之壓阻效應，導致載子移動率上升，最終形成排除區(Keep Out Zone, KOZ)，這對元件性能及可靠性造成影響。
本研究的主要目的是探討在熱製程下，藉由參數調整TSV直徑、TSV深寬比、TSV間距直徑比及TSV斜角，採用有限元素分析對TSV進行模擬，並利用壓阻效應分別計算n-MOS與p-MOS元件在矽晶格 [100]與[110]的方向，TSV的參數因子對應力分布及載子移動率影響與排除區變化，最後應用田口方法進行數據整理和變異分析。
結果顯示，矽晶格方向[100]影響最大為TSV斜角，矽晶格方向[110]影響最大為TSV深寬比，而兩者影響最小為導孔直徑。透過田口方法優化，[100]p-MOS、[100]n-MOS、[110]n-MOS和[110]p-MOS最大載子遷移率分別降低了3.76%、7.13%、17.85%和5.89%，有效增加晶片的使用面積，進一步實現晶片輕薄短小化。

Over the past few decades, the semiconductor industry has continuously followed Moore's Law to progressively increasing circuit density. However, as the process of miniaturization (more Moore) faces physical limits, the industry has begun to develop the path of "more than Moore" to achieve heterogeneous integration and three-dimensional (3D) stacking of chips. Through silicon via (TSV) technology is a key technology for vertical connections between chips. By utilizing metal connections within the vias, TSV not only allows for size reduction but also facilitates 3D stacking and heterogeneous integration. On the other hand, the mismatch of thermal expansion coefficients (CTEs) among TSV materials could lead to reliability issues such as bump failures and delamination. Additionally, thermal stresses can induce a piezoresistive effect on the silicon lattice, resulting in increased carrier mobility and eventually forming the keep-out zones (KOZs) which negatively impact device minimization and reliability.
  The main objective of this study is to utilize finite element analysis and the Taguchi method to investigate the effects of TSV parameters on thermal stress distribution and carrier mobilities. By applying the piezoresistive effect formula, the study analyzes n-MOS and p-MOS devices oriented in the silicon lattice directions [100] and [110]. The TSV parameters studied include diameter, depth-to-width ratio, pitch-to-diameter ratio, and tapering angle.
The results indicate that for the [100] silicon lattice direction, the most significant factor is the TSV angle; whereas for the [110] direction, the most influential factor is the depth-to-width ratio; the least influential factor for both directions is the via diameter. Through Taguchi optimization, the maximum carrier mobility for [100]p-MOS, [100]n-MOS, [110]n-MOS, and [110]p-MOS is reduced by 3.76%, 7.13%, 17.85%, and 5.89%, respectively, effectively increasing the usable integration area of the chip.

[1]G. E. Moore, "Cramming More Components Onto Integrated Circuits," Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, (1998).
[2]C. A. Mack, "Fifty Years of Moore's Law," IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 2, pp. 202-207, (2011).
[3]S. Bertolazzi, "Memory Packaging," Yole Développement (2021).
[4]Semiwiki, "Semiconductor Packaging History and Primer," (2022).
[5]DigiKey, "Ｍini DIP," from https://www.digikey.tw/zh/products/detail/stmicroelectronics/UC3842BN/634843, (2022).
[6]Wikipedia, "Dual in-line package," from http://www.szgoco.com/89.html, (2023).
[7]"TEXAS INSTRUMENTS," from https://www.ti.com/zh-tw/homepage.html, (2022).
[8]"ASE Kaohsiung," from https://asekh.aseglobal.com/ch/products-services/wire-bond.html.
[9]Z. Bao, W. Zhong, and W. Xiangjun, "Technology of Stacking Vertical Interconnecting Micro-Assembly," 2007 International Symposium on High Density packaging and Microsystem Integration, pp. 1-4, (2007).
[10] F. P. Carson, Y. C. Kim, and I. S. Yoon, "3-D Stacked Package Technology and Trends," Proceedings of the IEEE, vol. 97, no. 1, pp. 31-42, (2009).
[11] P. S. A. J. U. Knickerbocker, B. Dang,R. R. Horton,M. J. Interrante,C. S. Patel,R. J. Polastre,K. Sakuma,R. Sirdeshmukh,E. J. Sprogis,S. M. Sri-Jayantha,A. M. Stephens,A. W. Topol,C. K. Tsang,B. C. Webb,S. L. Wright, "Three-dimensional silicon integration," IBM Journal of Research and Development, vol. 52, no. 6, pp. 553-569, (2008).
[12] R. Fontaine, "Innovative Technology Elements for Large and Small Pixel CIS Devices," (2017).
[13] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps," IEEE Transactions on Advanced Packaging, vol. 32, no. 4, pp. 720-728, (2009).
[14] R. R. X. Zhang, C. S. Selvanayagam,C. S. Premachandran,W. K. Choi,S. W. Ho,S. W. Ong,L. Xie,D. Pinjala,V. N. Sekhar,D. L. Kwong, "A low stress bond pad design for low temperature solder interconnections on through silicon vias (TSVs)," 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), pp. P1657-1663, (2010).
[15] L. Jiang, Y. Liu, L. Duan, Y. Xie, and Q. Xu, "Modeling TSV open defects in 3D-stacked DRAM," 2010 IEEE International Test Conference, pp. 1-9, (2010).
[16] S. E. Thompson, S. Guangyu, C. Youn Sung, and T. Nishida, "Uniaxial-process-induced strained-Si: extending the CMOS roadmap," IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1010-1020, (2006).
[17] P. S. H. M. Y. Tsai, C. Y. Huang,H. Jao,B. Huang,B. Wu,Y. Y. Lin,W. Liao,J. Huang,L. Huang,S. Shih,J. P. Lin, "Investigation on Cu TSV-Induced KOZ in Silicon Chips: Simulations and Experiments," IEEE Transactions on Electron Devices, vol. 60, no. 7, pp. 2331-2337, (2013).
[18] J. Zhang, M. O. Bloomfield, J.-Q. Lu, R. J. Gutmann, and T. S. Cale, "Thermal stresses in 3D IC inter-wafer interconnects," Microelectronic Engineering, vol. 82, no. 3, pp. 534-547, (2005).
[19] S. Y. P. Dixit, J. Miao, J. H. Pang, R. Chatterjee, and R. R. Tummala, "Numerical and experimental investigation of thermomechanical deformation in high-aspect-ratio electroplated through-silicon vias," Journal of the Electrochemical Society, vol. 155, no. 12, pp. 981-986, (2008).
[20] N. Ranganathan, K. Prasad, N. Balasubramanian, and K. L. Pey, "A study of thermo-mechanical stress and its impact on through-silicon vias," Journal of Micromechanics and Microengineering, vol. 18, no. 7, pp. 18-75, (2008).
[21] L. Xi, C. Qiao, D. Pradeep, C. Ritwik, R. R. Tummala, and S. K. Sitaraman, "Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)," 2009 59th Electronic Components and Technology Conference, pp. 624-629, (2009).
[22] J. S. Yang, K. Athikulwongse, Y. J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," Design Automation Conference, pp. 803-806, (2010).
[23] K. Athikulwongse, A. Chakraborty, J. S. Yang, D. Z. Pan, and S. K. Lim, "Stress-driven 3D-IC placement with TSV keep-out zone and regularity study," 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 669-674, (2010).
[24] S. K. Ryu, K. H. Lu, X. Zhang, J. H. Im, P. S. Ho, and R. Huang, "Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects," IEEE Transactions on Device and Materials Reliability, vol. 11, no. 1, pp. 35-43, (2011).
[25] C. Zhang and L. Li, "Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling," IEEE Transactions on Electron Devices, vol. 58, no. 2, pp. 279-287, (2011).
[26] M. Jung, D. Z. Pan, and S. K. Lim, "Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs," DAC Design Automation Conference 2012, pp. 317-326, (2012).
[27] E. J. Cheng and Y. L. Shen, "Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging," Microelectronics Reliability, vol. 52, no. 3, pp. 534-540, (2012).
[28] C. C. Lee, Yang, T. F.,Wu, C. S.,Kao, K. S.,Fang, C. W.,Zhan, C. J.,Lau, J. H.,Chen, T. H., "Impact of high density TSVs on the assembly of 3D-ICs packaging," Microelectronic Engineering, vol. 107, pp. 101-106, (2013).
[29] Y. Zhu, J. Zhang, H. Y. Li, C. S. Tan, and G. Xia, "Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations," IEEE Transactions on Device and Materials Reliability, vol. 15, no. 2, pp. 142-148, (2015).
[30] H.-Y. Tsai and C.-W. Kuo, "Thermal Stress and Failure Location Analysis for Through Silicon via in 3D Integration," Journal of Mechanics, vol. 32, no. 1, pp. 47-53, (2015).
[31] Y. Pan, F. Li, H. He, J. Li, and W. Zhu, "Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging," Microelectronics Reliability, vol. 70, pp. 97-102, (2017).
[32] Y. Zhang, J. Wang, and S. Yu, "Thermal Stress Analysis and Design Guidelines for Through Silicon Via Structure in 3D IC Integration," 2018 19th International Conference on Electronic Packaging Technology (ICEPT), pp. 883-885, (2018).
[33] Z. F. F. Huang, X. Chen,Y. Liu,S. Zhang,Y. Wang,Y. Jiang, "Research on TSV Thermal-mechanical Reliability Based on Finite Element Analysis," 2019 Prognostics and System Health Management Conference (PHM-Qingdao), pp. 1-8, (2019).
[34] C. C. Sahu, S. Chandrakar, and M. K. Majumder, "Signal Transmission and Reflection Losses of Cylindrical and Tapered shaped TSV in 3D Integrated Circuits," 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp. 44-47, (2020).
[35] G. Jalilvand, O. Ahmed, N. Dube, and T. Jiang, "The Effect of Pitch Distance on the Statistics and Morphology of Through-Silicon Via Extrusion," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 6, pp. 883-891, (2021).
[36] B. Zou, X. Ren, X. Cai, G. Sun, Y. Cui, and Z. Huang, "Thermal-Mechanical Analysis of TSV Array in 2.5D Silicon Interposer," 2022 23rd International Conference on Electronic Packaging Technology (ICEPT), pp. 1-6, (2022).
[37] J. P. Gambino, S. A. Adderly, and J. U. Knickerbocker, "An overview of through-silicon-via technology and manufacturing challenges," Microelectronic Engineering, vol. 135, pp. 73-106, (2015).
[38] J. Vitiello and F. Piallat, "Alternative Deposition Solution for Cost Reduction of TSV Integration," 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), pp. 2163-2167, (2018).
[39] B. D. C. Laviron, V. Lapras,P. Galbiati,D. Henry,F. Toia,S. Moreau,R. Anciant,C. Brunet-Manquat,N. Sillon, "Via first approach optimisation for Through Silicon Via applications," 2009 59th Electronic Components and Technology Conference, pp. 14-19, (2009).
[40] D. V. A. Redolfi, S. Thangaraju,P. Nolmans,P. Jaenen,M. Kostermans,U. Baier,E. Van Besien,H. Dekkers,T. Witters,N. Jourdan,A. Van Ammel,K. Vandersmissen,S. Rodet,H. G. G. Philipsen,A. Radisic,N. Heylen,Y. Travaly,B. Swinnen,E. Beyne, "Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers," 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp. 1384-1388, (2011).
[41] M. S. S. Van Huylenbroeck, Y. Li,J. Slabbekoorn,N. Tutunjyan,S. Sardo,N. Jourdan,L. Bogaerts,F. Beirnaert,G. Beyer,E. Beyne, "Small Pitch, High Aspect Ratio Via-Last TSV Module," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), pp. 43-49, (2016).
[42] T. Pandhumsoporn, L. Wang, M. R. Feldbaum, P. Gadgil, M. Puech, and P. Maquin, "High-etch-rate deep anisotropic plasma etching of silicon for MEMS fabrication," Smart Structures, (1998).
[43] G. Fengjie, R. J. Yang, W. Shuo, M. Kui, and Y. F. Shun, "Preparation of Uniform SiO2 Insulating Layer on the Inner Wall of TSV by Thermal Oxidation," 2022 International Symposium on Semiconductor Manufacturing (ISSM), pp. 1-3, (2022).
[44] S. L. R. Liang, Y. Miwa,K. Kumahara,M. Mariappan,H. Kino,T. Fukushima,T. Tanaka, "Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation," 2019 International 3D Systems Integration Conference (3DIC), pp. 1-4, (2019).
[45] L. Hofmann, R. Ecke, S. E. Schulz, and T. Gessner, "Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives," Microelectronic Engineering, vol. 88, no. 5, pp. 705-708, (2011).
[46] L. Ji, F. X. Che, H. M. Ji, H. Y. Li, and M. Kawano, "Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 12, pp. 2106-2117, (2020).
[47] D. F. L. England, K. Rivera,B. Guthrie,P. J. Kuo,C. C. Lee,C. M. Hsu,F. Y. Min,K. C. Kang,C. Y. Weng, "Die-to-Wafer (D2W) Processing and Reliability for 3D Packaging of Advanced Node Logic," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), pp. 600-606, (2019).
[48] R. E. Hummel, "Electronic Properties of Materials.," (2011).
[49] R. C. Jaeger, J. C. Suhling, and A. A. Anderson, "A [100] silicon stress test chip with optimized piezoresistive sensor rosettes," 1994 Proceedings. 44th Electronic Components and Technology Conference, pp. 741-749, (1994).
[50] C.-O. Chang, G.-E. Chang, C.-S. Chou, W.-T. C. Chien, and P.-C. Chen, "In-plane free vibration of a single-crystal silicon ring," International Journal of Solids and Structures, vol. 45, no. 24, pp. 6114-6132, (2008).
[51] E. Harnik, "Measurement of Space‐Charge‐Limited Current Characteristics in High‐Resistivity Materials," Journal of Applied Physics, vol. 36, no. 12, pp. 3850-3852, (1965).
[52] S. R. J. J. Y. Yan, Y. C. Huang,H. S. Lan,C. W. Liu,Y. H. Huang,B. Hung,K. T. Chan,M. Huang,M. T. Yang, "Compact modeling and simulation of TSV with experimental verification," 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 1-2, (2016).
[53] H.-H. Lee, Finite Element Simulations with ANSYS Workbench 2022. (2022).
[54] T. L. B. T. L. Bergman, F. P. Incropera, D. P. Dewitt, and A. S. Lavine, Fundamentals of Heat and Mass Transfer. (2011).
[55] H.-H. Lee, Taguchi Methods: Principles and Practices of Quality Design. Gau Lih Book Co, (2020).
[56] M. Moore, "International roadmap for devices and systems,," (2020).
[57] "Ansys_Meshing_Users_Guide.pdf," (2021).
[58] L. Ji, X. Jing, K. Xue, C. Xu, H. He, and W. Zhang, "Effect of annealing after copper plating on the pumping behavior of through silicon vias," 2014 15th International Conference on Electronic Packaging Technology, pp. 101-104, (2014).
[59] W. H. Li, "Reducing TSV dimensions by Taguchi Method," thises,Department of Engineering Science National Cheng Kung University, pp.1-74, (2017).
[60] P. T. Shen, "Analysis of TSV Parametric Effects," thises,Department of Engineering Science National Cheng Kung University, pp.1-72, (2023).
[61] S. K. Ryu, K. H. Lu, T. Jiang, J. H. Im, R. Huang, and P. S. Ho, "Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration," IEEE Transactions on Device and Materials Reliability, vol. 12, no. 2, pp. 255-262, (2012).