本論文之晶片皆採用TSMC CMOS 90-nm製程研製，電路使用Agilent ADS與全波電磁模擬軟體進行設計，量測方式皆採on-wafer形式。論文第一部份設計一94-GHz CMOS使用變壓器耦合疊接架構之低LO功率、高增益主動混頻器，使用弱反轉區偏壓技術降低LO功率，開關級與轉導級間使用壓器耦合疊接架構以共振電晶體之寄生電容，達到低雜訊之設計目標，並於輸出級使用轉阻放大器提升增益同時完成阻抗匹配，電路之差動訊號皆使用自行設計之馬遜平衡器饋入。第二部份為一寬頻且具高線性度升頻混頻器之研製，架構選擇雙平衡以提高隔離度與諧波抑制能力，於轉導級採用一改良架構，將共源級形式之轉導級加上交叉耦合共閘極路徑降低寬頻匹配之難度與提高線性度，電路各埠皆使用變壓器形式平衡器饋入差動訊號，相比馬遜平衡器有較小的插入損耗，並在饋入訊號的同時提供直流電流路徑。第三部份研製一使用非對稱式混頻器之90-100GHz毫米波整合射頻收發機晶片，包含低雜訊放大器、功率放大器、射頻開關與非對稱式混頻器。功率放大器與低雜訊放大器皆為疊接架構並同樣串聯五級以提升增益與隔離度，功率放大器輸出匹配網路為一改良式射頻開關，可提升發射機模式的輸出功率與增益。於低雜訊放大器前兩級的疊接電晶體之間加入電感來最佳化雜訊匹配。混頻器為雙平衡架構提供高隔離度與偶次諧波項抑制能力，於接收與發射機模式共用一開關級並透過偏壓切換工作模式，開關級於升頻時採主動式混頻，提高轉換增益與輸出飽和功率；在降頻時採被動式混頻並由共源極放大器與轉阻放大器提供轉換增益。

This thesis presents the design of two 94-GHz millimeter-wave mixers and a millimeter-wave integrated RF transceiver, which are both implemented by the standard TSMC 90-nm GUTM CMOS process. The first part of the thesis is a design of a 94-GHz low-LO-power and high-gain down-conversion mixer, by using the weak-inversion bias technique at the core of the mixer to reduce LO driven power. By the connection of a transformer between the switch stage and trans-conductance stage, the parasitic capacitance of the transistor can be resonated to achieve the design goal of a low noise figure. A trans-impedance amplifier (TIA) is merged directly with the mixer core to enhance the conversion gain and completing the impedance matching at the same time. In the following part, an up-conversion mixer with high linearity and wideband IF impedance matching is presented, by adopting a transconductance stage which added a cross-coupled common-gate path in the conventional common-source path. In addition, a transformer-based balun is connected at the RF port, which worked as an inductive load stage and completes the output matching. The last part is the design of a 90-100 GHz CMOS RF transceiver, which consists of a power amplifier (PA), a low-noise amplifier (LNA), a bidirectional asymmetric mixer, and a transmit-receive (T/R) switch. The PA and the LNA both having a five-stage cascode structure in cascade to enhance the performance of power gain and isolation. The output matching network of the PA has been modified to improve the performance in transmitter mode. An inductance has been added between the cascade transistors of the first and the second stage of the LNA to optimize noise matching. The bidirectional asymmetric mixer shares a switch stage in different modes, which control through bias voltage. The measurement of these chips is all conducted by fully on-wafer probing.

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