本論文提出以共濺鍍技術改善薄膜電晶體之介電層與通道層，並進行其元件電特性量測、分析與可靠度之研究。
本研究主要分為兩部分，第一部分為延續本實驗室先前研究之氧化矽鋯介電層於氧化銦鎵鋅薄膜之應用，進一步探究其之可靠度特性，並設計二氧化鋯與二氧化矽介電層之堆疊結構，以分析不同材料界面於元件可靠度之影響；第二部分以共濺鍍製程技術結合氧化銦鎵鋅與二氧化鈦製備鈦摻雜氧化銦鎵鋅薄膜(Ti-doped IGZO)，藉由調變濺鍍功率之比例，調整材料組成與特性，並進一步分析其應用於薄膜電晶體之電特性與可靠度。此外，為進一步提升元件特性，本論文亦討論鈦摻雜氧化銦鎵鋅通道層經沉積後退火製程(post deposition annealing, PDA)對材料特性、電特性與可靠度等之影響。
於本論文第一部分，首先探討觀察二氧化鋯與二氧化矽之介電層堆疊結構應用於氧化銦鎵鋅薄膜電晶體時，不同的界面於電性與可靠度之影響。由實驗結果得知，二氧化矽與氧化銦鎵鋅有較優異的界面品質與較少的界面缺陷，證實藉由適當含量之Si元素的摻入，有助於減少通道層/介電層之界面缺陷密度。本研究進一步針對此元件進行可靠度之分析，其最大臨界電壓的偏移分別從原先的1.165 V與-0.898 V改善至0.776與-0.491 V，元件可靠度獲得大幅的改善。
於本論文第二部分，為改善氧化銦鎵鋅薄膜之高缺陷密度，藉由摻入易氧化之鈦元素抑制氧空缺的產生，以提升氧化銦鎵鋅通道層之薄膜品質。實驗結果顯示，因鈦元素具易氧化之材料特性，進而捕捉氧氣以填補薄膜的氧空缺，透過共濺鍍方式摻入於氧化銦鎵鋅薄膜，可使氧化銦鎵鋅薄膜之能隙增加與施體能階減少，可進一步抑制漏電流。此外，經由鈦元素之摻雜，可使氧化銦鎵鋅薄膜之缺陷密度降低，改善元件可靠度。而具鈦摻雜之氧化銦鎵鋅薄膜，不易因退火製程而造成氧原子脫離而形成氧空缺，因此可承受較高溫環境下的退火修補與活化，進一步改善其電特性與可靠度。
本論文所開發之鈦摻雜氧化銦鎵鋅薄膜電晶體，由實驗結果顯示，摻入適量鈦元素之氧化銦鎵鋅，除了改善薄膜的品質更有助於減少介電層/通道層界面之缺陷密度，其中以具鈦摻雜比例為1.0 %之鈦摻雜氧化銦鎵鋅通道層的薄膜電晶體，經400°C氮氣環境下的退火，可獲得最佳電晶體特性與可靠度：於電特性部份，其元件電流開關比為1.65×10^8、次臨界擺幅為90 mV/dec、載子遷移率為24.2 cm^2/V∙s、界面缺陷密度為1.09×10^12 cm^-2eV^-1；於可靠度部分，正負偏壓應力之臨界電壓偏移分別為0.157 V和-0.093 V。此實驗結果已達成本論文於改善氧化銦鎵鋅薄膜電晶體之元件電特性與可靠度之標的。
本論文成功以共濺鍍製備鈦摻雜氧化銦鎵鋅通道層並應用及改善薄膜電晶體之界面品質、閘極控制能力與元件可靠度，及有助於未來顯示技術之電子產品特性提升與應用。

The use of a co-sputtered Titanium doped indium gallium zinc oxide (Ti-IGZO) channel with zirconium silicon oxide (Zr0.85Si0.15O2) as gate dielectrics to improve reliability of thin-film transistors (TFTs) is presented. Experimentla studies reveal that oxygen vacancies in post deposition annealed (PDA) Ti-IGZO Channel is decreased after Ti incorporation and stability of the TFTs could be considerably improved. It is attributed to Ti is with a stong oxidibility which leads to bandgap enlargement, donor energy level lowering, and trap state density suppression for the Ti-IGZO channel. Experimental results reveal that Ti-IGZO channel prepared at a power ratio of IGZO:TiO2=80 W:25 W with a PDA at 400°C and with a 9±1-nm-EOT Zr0.85Si0.15O2 layer shows the best device performance with the on/off current ratio, the subthreshold swing, the threshold voltage shift after 1000 sec positive/negative gate-bias stress are of 1.65×10^8, 0.09 V/dec, and 0.157 V/-0.093 V, respectively.

[1] G. H. Heilmeier, L. A. Zanoni, and L. A. Barton, “Dynamic scattering: A new electrooptic effect in certain classes of nematic liquid crystals,” Proceedings of the IEEE, vol. 56, no. 7, pp. 1162-1171, 1968.
[2] T. P. Brody, J. A. Asars, and G. D. Dixon, “A 6 × 6 inch 20 lines-per-inch liquid-crystal display panel,” IEEE Transactions on Electron Devices, vol. 20, no. 11, pp. 995-1001, 1973.
[3] H. Kimura, T. Maeda, T. Tsunashima, T. Morita, H. Murata, S. Hirota, and H. Sato, “A 2.15 inch QCIF reflective color TFT-LCD with digital memory on glass (DMOG),” Proceedings of the SID, vol. 32, no. 1, pp. 268-270, 2001.
[4] S. B. Ogale, Thin films and heterostructures for oxide for oxide electronics, New York, NY: Springer, 2005.
[5] Jang-Yeon Kwon, Review Paper: Transparent Amorphous Oxide Semiconductor Thin Film Transistor, Vol. 7, No. 1, pp. 1-11, 2011.
[6] Y.Q. Fu, Recent developments on ZnO films for acoustic wave based bio-sensing and microfluidic applications: a review, Sensors and Actuators B: Chemical, 2009.
[7] Ü. Özgür, A comprehensive review of ZnO materials and devices, JOURNAL OF APPLIED PHYSICS, Vol. 98, Artical ID 041301, 2005.
[8] G. Neumann, “On the defect structure of zinc-doped zinc oxide,” Physica Status Solidi (b), vol. 105, no. 2, pp. 605-612, 1981.
[9] H. Hosono, “Ionic amorphous oxide semiconductors: Material design, carrier transport, and device application,” Journal of Non-Crystalline Solids, vol. 352, no. 9, pp. 851-858, 2006.
[10] T. C. Fung, C. S. Chuang, K. Nomura, H. P. D. Shieh, H. Hosono, and J. Kanicki, “Photofield-effect in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors,” Journal of Information Display, vol. 9, no. 4, pp. 21-29, 2008.
[11] M. Kim, J. H. Jeong, H. J. Lee, T. K. Ahn, H. S. Shin, J.-S. Park, Jae Kyeong Jeong, Y.-G. Mo, and H. D. Kim, “High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper,” Applied physics letters, vol. 90, no. 21, Artical ID 212114, 2007.
[12] N. C. Su, S. J. Wang, and A. Chin, “High-performance InGaZnO thin-film transistors using HfLaO gate dielectric” IEEE Electron Device Letters, vol. 30, no. 12, pp. 1317-1319, 2009.
[13] H. Hosono, “Ionic amorphous oxide semiconductors: Material design, carrier transport, and device application,” Journal of Non-Crystalline Solids, vol. 352, no. 9, pp. 851-858, 2006.
[14] Gang He, “High-k Gate Dielectrics for CMOS Technology,” Weinheim, Germany, 2012, Ch.1.
[15] Gang He, “High-k Gate Dielectrics for CMOS Technology,” Weinheim, Germany, 2012, Ch.2.
[16] S. Mohsenifar and M. H. Shahrokhabadi,” Gate Stack High-κ Materials for Si-Based MOSFETs Past, Present, and Futures,” Microelectronics and Solid State Electronics, vol. 4, no. 1, pp. 12-24, 2015.
[17] B. Cheng, M. C. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. Stork, M. Zeitzoff, and J. C. Woo, “The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1537-1544, 1999.
[18] Guha, S., “High-k/metal gate science and technology,” Annu. Rev.Mater. Res., vol. 39, pp. 181, 2009.
[19] Ando, T., “Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process.,” IEDM Technical Digest, pp. 423, 2009.
[20] H.-L. Lu and D. W. Zhang, “Issues in High-k Gate Dielectrics and its Stack Interfaces,” High-k Gate Dielectrics for CMOS Technology, Weinheim, Germany, Wiley-VCH Verlag GmbH & Co. KGaA, pp. 31-59, 2012.
[21] H. Chakraborty and D. Misra, “Characterization of High-K Gate Dielectrics using MOS Capacitors,” International Journal of Scientific and Research Publications, vol. 3, no. 12, pp. 1-5, 2013.
[22] X. Zhao and D. Vanderbilt, “First-principles study of structural, vibrational, and lattice dielectric properties of hafnium oxide,” Physical Review B, vol. 65, no. 23, Artical ID 233106, 2002.
[23] B. Lee, L. Kang, R. Nieh, W. Qi, and J. Lee, “Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing,” Applied physics letters, vol. 76, no. 14, pp. 1926-1928, 2000.
[24] H. Kim, P. McIntyre, C. Chui, K. Saraswat, and S. Stemmer, “Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer,” Journal of Applied Physics, vol. 96, no. 6, pp. 3467-3472, 2004.
[25] S. Mohsenifar and M. H. Shahrokhabadi, “Gate Stack High-κ Materials for Si-Based MOSFETs Past, Present, and Futures”, Microelectronics and Solid State Electronics, vol.4, no. 1, pp. 12-24, 2015.
[26] J. C. Park, I.-T. Cho, E.-S. Cho, D. H. Kim, C.-Y. Jeong, and H.-I. Kwon, “Comparative Study of ZrO2 and HfO2 as a High-κ Dielectric for Amorphous InGaZnO Thin Film Transistors,” Journal of Nanoelectronics and Optoelectronics, vol. 9, pp. 67-70, 2014.
[27] Ju Heyuck Baeck and Ju Heyuck Baeck, “Comparison of Top-Gate and Bottom-Gate Amorphous InGaZnO Thin-Film Transistors With the Same SiO2/a-InGaZnO/SiO2 Stack,” IEEE Device Letters, vol. 35, no. 10, 2014.
[28] Chenming Calvin, Modern Semiconductor Devices for Integrated Circuits, Prentice Hall, Ch. 5, pp. 1-12, 2010.
[29] S. D. Brotherton, Introduction to Thin Film Transistors: Physics and Technology of TFTs, TFT Consultant, Forest Row, E. Sussex, UK, pp. 63-64, 2013.
[30] S. Jun, C. Jo, H. Bae, H. Choi, D. H. Kim, and D. M. Kim, “Unified subthreshold coupling factor technique for surface potential and subgap density-of-states in amorphous thin film transistors,” IEEE Electron Device Letters, vol. 34, no. 5, pp. 641-643, 2013.
[31] J. H. Park, K. Jeon, S. Lee, S. Kim, S. Kim, I. Song, C. J. Kim, J. Park, Y. Park, D. M. Kim, and D. H. Kim, “Extraction of density of states in amorphous GaInZnO thin-film transistors by combining an optical charge pumping and capacitance–voltage characteristics,” IEEE Electron Device Letters, vol. 29, no.12, pp. 1292-1295, 2008.
[32] Wong HS, White MH, Krutsick TJ, and Booth RV. “Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET’s,” Solid-State Electron, vol. 30, pp. 953, 1987.
[33] Jain S. “Measurement of threshold voltage and channel length of submicron MOSFETs,” IEEE Proc Cir Dev Syst, pp. 135-162, 1988.
[34] D. K. Schroder, Semiconductor material and device characterization, 2nd edition, Wiley, New York, pp. 367-369, 1998.
[35] S. J. Yun, J. B. Koo, J. W. Lim, and S. H. Kim, “Pentacene-Thin Film Transistors with ZrO2 Gate Dielectric Layers Deposited by Plasma-Enhanced Atomic Layer Deposition,” Electrochemical and Solid-state Letters, vol. 10, no. 3, pp. H90-H93, 2007.
[36] S. D. Brotherton, Introduction to Thin Film Transistors: Physics and Technology of TFTs, TFT Consultant, Forest Row, E. Sussex, UK, pp. 63-64, 2013.
[37] Terada K., Nishiyama K. and Hatanaka KI., “Comparison of MOSFET-threshold-voltage extraction methods,” Solid- State Electron, vol. 45, pp. 35-40 , 2001.
[38] E. S. Yang, “Microelectronic Devices,” McGraw-Hill, Singapore, 1988.
[39] D. K. Schroder, “Semiconductor Material and Device Characterization,” John Wiley & Sons. Inc., New Jersey, 2006.
[40] A. C. Tickle, “Thin-Film Transistors - A New Approach to Microelectronics,” Wiley, New York, 1969.
[41] David Vernon Morgan, Kamel D. and Al-Baidhawi, “Standardized Terminology for Oxide Charges Associated with Thermally Oxidized Silicon,” IEEE, vol. 27, pp. 606-608, 1980.
[42] S. M. Sze and M. K. Lee, “Semiconductor Devices Physics and Technology,” 3rd edition, Hoboken, N.J., Wiley, pp. 259-281, 2006.
[43] Y. C. Cheng, “Electronic states at the silicon-silicon dioxide interface,” Progress in Surface Science, vol.8, pp. 181, 1977.
[44] S. M. Sze and M. K. Lee, “Semiconductor Devices Physics and Technology,” 3rd edition, Hoboken, N.J., Wiley, pp. 238-239, 2012.
[45] Edward Namkyu Cho, “Analysis of Bias Stress Instability in Amorphous InGaZnO Thin-Film Transistors,” IEEE, pp. 112-117, 2010.
[46] C. van Berkel and M. J. Powell, “Resolution of amorphous silicon thin‐film transistor instability mechanisms using ambipolar transistors,” Appl. Phys. Lett., vol.51, Artical ID 1094 , 1987.
[47] A. Suresh, “Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors,” Appl. Phys. Lett., Vol. 92, Artical ID 033502, 2008.
[48] Geng-Wei Chang, “Suppress temperature instability of InGaZnO thin film transistors by N2O plasma treatment including thermal-induced hole trapping phenomenon under gate bias stress,” Appl. Phys. Lett., Vol. 100, Artical ID 82103, 2012.
[49] T. C. Fung, G. Baek, and J. Kanicki, “Low frequency noise in long channel amorphous In-Ga-Zn-O thin film transistors,” Journal of Applied Physics, vol. 108, no.7, Artical ID 074518, 2010.
[50] Martin von Haartman and Mikael Östling, LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES, Springer , Ch. 1, pp. 5-13, 2007.
[51] L. X. Qian, X. Z. Liu, C. Y. Han, and P. T. Lai, “Improved Performance of Amorphous InGaZnO Thin-Film Transistor With Ta2O5 Gate Dielectric by Using La Incorporation”, IEEE Transactions on Device and Materials Reliability, vol. 14, no. 4, pp. 1056-1060, 2014.
[52] J. C. Park, S. I. Kim, C. J. Kim, S. Kim, D. H. Kim, I. T. Cho, and H. I. Kwon, “Impact of High-k HfO2 Dielectric on the Low-Frequency Noise Behaviors in Amorphous InGaZnO Thin Film Transistors,” Japanese Journal of Applied Physics, vol 49, no. 10R, Artical ID 100205, 2010.
[53] UHV MAGNETRON SPUTTERING SYSTEM (MDS), http://www.adnano-tek.com/magnetron-sputtering-deposition-msd.html.
[54] T.M. Mukhametkaliyev, “A review of plasma-assisted methods for calcium phosphate-based coatings fabrication,” Surface and Coatings Technology, Ch. 1, pp. 10-14, 2007.
[55] 2012.
[55] J. Robertson and R. Wallace, “High-K materials and metal gates for CMOS applications,” Materials Science and Engineering: R: Reports, vol. 88, pp. 1-41, 2015.
[56] V. Mikhelashvili and G. Eisenstein, “Effects of annealing conditions on optical and electrical characteristics of titanium dioxide films deposited by electron beam evaporation,” Applied physics letters, vol. 89, no. 6, pp. 3256-3269, 2001.
[57] Ho Yong Chong and Kyu Wan Han, “Effect of the Ti molar ratio on the electrical characteristics of titanium-indium-zincoxide thin-film transistors fabricated by using a solution process,” Applied physics letters, vol. 99, Artical ID 161908, 2011.
[58] Gun Hee Kim and Woong Hee Jeong, “Investigation of the effects of Mg incorporation into InZnO for highperformance and high-stability solution-processed thin film transistors,” Applied physics letters, vol. 96, Artical ID 163506, 2010.
[59] Tetsufumi Kawamura, “Analysis of subthreshold slope of fully depleted amorphous In-Ga-Zn-O thin-film transistors,” Applied physics letters, vol. 106, Artical ID 013504, 2015
[60] Ho Yong Chong and Kyu Wan Han “Effect of the Ti molar ratio on the electrical characteristics of titanium-indium-zincoxide thin-film transistors fabricated by using a solution process,” Applied physics letters, vol. 99, Artical ID 161908, 2011.
[61] Gun Hee Kim and Woong Hee Jeong “Investigation of the effects of Mg incorporation into InZnO for high performance and high-stability solution-processed thin film transistors,” Applied physics letters, vol. 96, Artical ID 163506, 2010.
[62] Tung-Ming Pan and Ching-Hung Chen “Electrical and Reliability Characteristics of High-κ HoTiO3 α-InGaZnO Thin-Film Transistors, ”IEEE Electron Device Letters, vol. 35, pp. 166-168. , 2014.
[63] Jayapal Raja and Jayapal Raja “Negative gate-bias temperature stability of N-doped InGaZnO active-layer thin-film transistors,” Applied physics letters, vol. 102, Artical ID 083505, 2013.
[64] Bo-Yuan Su and Sheng-Yuan Chu “Improved Electrical and Thermal Stability of Solution-Processed Li-Doped ZnO Thin-Film Transistors, ” IEEE Transaction On Electron Devices, vol. 59, pp. 596-601. , 2012.
[65] Zhe Hu and Cheng yuan Dong “Thermal Stability of Amorphous InGaZnO Thin-Film Transistors With Different Oxygen-Contained Active Layers,” Journal Of Display Technology, vol. 11, pp. 610-614. , 2015.
[66] H.H. Hsu. and C.Y. Chang. “High performance IGZO/TiO2 thin film transistors using Y2O3 buffer layers on polycarbonate substrate,” Applied Physics A Materials Science & Processing , pp. 817-820. , 2013.