| 研究生: |
廖家煒 Liao, Jia-Wei |
|---|---|
| 論文名稱: |
桶狀扭曲之色彩濾波陣列影像修正電路實現 An Efficient VLSI Design of Barrel Distortion Correction for Color Filter Array Images |
| 指導教授: |
陳培殷
Chen, Pei-Yin |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 35 |
| 中文關鍵詞: | VLSI硬體架構 、桶狀扭曲轉正 、解馬賽克法 、色彩濾波陣列 |
| 外文關鍵詞: | VLSI architecture, barrel distortion correction, demosaicing, color filter array |
| 相關次數: | 點閱:172 下載:0 |
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廣角鏡頭因具有能在相同的圖像範圍內提供更多圖像資訊之特性,目前已經被運用在許多領域上面,例如:無人空拍機、內視鏡、衛星圖像、監視設備等等,然而廣角鏡所拍攝之圖像會產生桶狀的扭曲現象(barrel distortion),影響影像資訊的判讀。同時在數位相機中為了減少製造成本,經常會將成像以色彩濾波陣列方式表現,而為了將色彩濾波陣列還原成全彩圖像,需要對此色彩濾波陣列進行插補,而此方式便稱為解馬賽克法(demosaicing)。
桶狀扭曲轉正與解馬賽克法皆是數位相機中常需解決的問題,然現今文獻大多只針對桶狀扭曲轉正或解馬賽克法其一進行探討,並未研究兩種情形同時發生時的情形,因此本論文將提出一個結合桶狀扭曲轉正與解馬賽克法之演算法設計,在低成本的情形下有效提升成像品質,並將其實現成低成本高效能之硬體電路架構,以滿足需即時處裡的應用。
本論文提出一個低成本高品質結合桶狀扭曲轉正與解馬賽克的VLSI電路架構,藉由利用放射狀扭曲的特性和長度比例的相聯性,來修正每個扭曲像素的位置,並以修正像素之位置,結合色差平面與圖像紋理對插補通道進行補正,以達成在低成本實現上能夠具備良好的成像品質。此電路架構採用管線化方式實現,並使用TSMC 0.18μm標準元件庫進行合成。合成結果顯示,所需的邏輯閘數量為41093,並可達到200 MHz 之工作時脈。
Wide-angle lenses have been used in many fields, such as unmanned aerial cameras, endoscopes, satellite images, etc. However, those images taken by wide-angle lenses will cause barrel distortion, which affects human recognition. At the same time, to reduce the cost of digital cameras, the image is often represented as a color filter array (CFA). To restore the CFA image to a full-color image, we need to interpolate it, and this method is called demosaicing.
Both barrel distortion correction and demosaicing are common issues that need to be solved in digital cameras. However, most studies only discuss barrel distortion correction or demosaicing and have not considered those two situations simultaneously. This paper will propose a new barrel distortion correction and demosaicing combined algorithm with low complexity and high image quality. Then we implement it in a low-cost hardware method to meet the needs of real-time processing applications.
We propose a low-cost, high-performance pipelined VLSI architecture. The VLSI architecture is synthesized using TSMC 0.18 μm standard component library. The synthesis result shows that the required number of logic gates is 41093, and the operating speed can reach 200 MHz.
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