在這個日新月異的時代，人工智慧迅速蓬勃發展，對於類神經網路的元件要求也勢必提高，因此有了新興記憶體的出現，在原有的靜態隨機存取記憶體(SRAM)、動態隨機存取記憶體(DRAM)和快閃記憶體(Flash Memory)下，出現另一種可能性。而電阻式隨機存取記憶體(RRAM)就是新興記憶體的一種，除了功耗、速度和互補式金屬氧化物半導體(CMOS)製程相容的優勢外，也因其金屬、絕緣體、金屬(MIM)結構簡單，具有低成本的特性，被廣泛討論並使用。根據研究指出，現今電腦架構都是採用范紐曼架構，意旨資料運算和儲存是分開處理，導致功率消耗大多產生在運算單元與記憶體單元的資料傳輸，而不是運算。記憶體內運算是其中一種解決方式，直接在記憶體內運算，再傳輸到處理器做後續處理，可以減少功耗散失，以高效率的方式提升運算效能。這篇論文將會探討RRAM的簡易模型，並將其運用在Tensorflow框架模擬RRAM元件在類神經網路的效能。
這篇論文旨在探討利用硬體描述語言Verilog-A建立RRAM簡易模型，同時結合物理傳輸機制，輔以HSPICE模擬軟體測試I-V特性曲線及提供導電絲面積計算模型，RRAM的操作是透過輸入偏壓改變元件電阻，藉由內部絕緣層狀態使其呈現高低不同阻值。RRAM良好的線性增強和抑制特性，可以提供不同的電導值，模擬仿生網路之類比行為操作的能力，並利用Tensorflow框架模擬RRAM元件在類神經網路的辨識準確度以及功耗，再與其他不同材料的RRAM進行比較與探討。

In this rapidly changing era, artificial intelligence is experiencing rapid development, leading to an inevitable increase in the requirements for components of neural networks. As a result, emerging memory technologies have emerged. Under the existing categories of Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), and Flash Memory, another possibility has emerged. Resistive Random-Access Memory (RRAM) is one such emerging memory, known for its advantages in power consumption, speed, and compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) processes. Additionally, its simple Metal-Insulator-Metal (MIM) structure, comprising metal, insulator, and metal layers, contributes to its low-cost characteristics, making it widely discussed and utilized. According to research, modern computer architectures typically adhere to the Von Neumann architecture, meaning that data computation and storage are handled separately. As a result, most of the power consumption occurs in the data transmission between the computing unit and the memory unit, rather than the computing. Computing-in-memory is one solution to address this issue. By conducting computations directly within memory and then transferring the results to the processor for further processing, power dissipation can be reduced, thereby enhancing computational efficiency in an effective manner. This paper will explore a compact model of RRAM and apply it within the Tensorflow framework to simulate the performance of RRAM device.
This paper aims to explore the establishment of a compact model of RRAM using the hardware description language Verilog-A, while integrating physical transport mechanisms. Additionally, it will complement the HSPICE simulation software to test I-V characteristic curves and provide a model for calculating the conductive filament area. RRAM operates by changing the resistance of the device through input bias voltages, causing it to exhibit different resistance states due to the internal insulator layer. Due to RRAM's excellent linear potentiation and depression characteristics, it can provide different conductance values, enabling the simulation of analog behavior operations in bio-inspired networks. We will utilize the TensorFlow framework to simulate the recognition accuracy and power consumption of RRAM devices within neural networks. Subsequently, we will compare and discuss these results with RRAM devices made of different materials.

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