近年來針對以氧化物半導體作為通道材料的薄膜電晶體的研究已取得極大之進展，同時在商業化產品中也已出現以氧化銦鎵鋅薄膜電晶體作為主動式陣列之面板。預期在未來的面板產業整合於透明面板之邏輯系統的開發上，氧化物半導體，尤其以非晶態氧化銦鎵鋅為主的通道薄膜，因載子移動率較非晶矽為高、可允許低溫製程、適合應用於大面積及軟性電子應用，將扮演舉足輕重的角色。
為改善氧化物半導體薄膜電晶體的電性效能，包含降低操作電壓、提升載子遷移率、抑制元件漏電流、提升閘極操作能力以及拓展氧化物半導體元件的應用範疇，本論文將針對薄膜電晶體之源/汲極、閘極介電層與通道層等主要結構進行優化。於優化薄膜電晶體之源/汲極方面，藉由加入一層具高載子濃度之緩衝層，改善源/汲極與通道層之接觸阻抗，進而改善元件電特性。基於氧化銦鎵鋅薄膜電晶體為一常通(normally on, NO)結構，本論文提出一蕭基源極結構，藉由蕭基能障阻擋通道漏電流，以降低元件之關閉電流，進而提升元件開關比與調整關閉電壓。另一方面，本論文亦使用共濺鍍沉積技術，開發氧化矽鋯介電層與具鈦摻雜之氧化銦鎵鋅通道層。於氧化矽鋯介電層部分，藉由將適當含量之矽元素摻入氧化鋯介電層中，改善氧化鋯介電層之薄膜品質與介電層/通道層之介面缺陷，提升元件之電特性與可靠度。於鈦摻雜之氧化銦鎵鋅通道層部分，因氧化銦鎵鋅薄膜具有極高的缺陷密度，嚴重影響其與介電層之介面品質，本論文利用共濺鍍技術，結合TiO2與IGZO靶材，調整適當的沉積比例，改善氧化銦鎵鋅通道層之薄膜與介面品質。實驗結果顯示，經400 oC氮氣環境下的退火，可獲得於本研究之通道優工程項目的最佳電晶體可靠度。於電特性部份，其元件電流開關比為1.65×10^8、次臨界擺幅為90 mV/dec、載子遷移率為24.2 cm^2/Vs、界面缺陷密度為1.09×10^12 cm^(-2)eV^(-1)；於可靠度部分，正負偏壓應力之臨界電壓偏移分別為0.157 V和-0.093 V。
本論文所開發之源/汲極優化工程，藉由加入緩衝層結構改善源/汲極接觸阻抗，亦開發蕭基源極結構降低於關閉狀態之通道漏電流。此外，透過共濺鍍技術之薄膜沉積功率比例，可調整所製備薄膜之材料組成與特性，藉由適當共濺鍍參數，可開發具低缺陷密度之閘極介電層及通道層材料，改善介面品質以提升閘極於通道之控制能力。本論文所提出之優化結構與新穎半導體材料，將有機會於未來使用在包含系統面板、有機發光二極體面板與可撓式裝置之應用上，並擴大非矽基材料之終端產品應用範疇。

Researches on oxide-semiconductor-based thin-film transistors (TFTs) have advanced remarkably in recent years. Commercial display products using indium gallium zinc oxide (IGZO) active arrays have also been successfully demonstrated. It is highly expected that the oxide semiconductor could have a high potential for using in display and system-on-panel application. In order to improve the electrical performance of IGZO TFTs, various technologies or schemes have been reported to lower driving-voltage, enhance carrier mobility, reduce leakage current, and improve gate control ability. In the present dissertation, to further polish the performance of IGZO TFTs, the optimized engineering of source/drain (S/D) contact, gate dielectrics, and channel of IGZO TFT is demonstrated. In the part of S/D contact, the sputtered ZnO buffer layer (BL) sandwiched between the S/D electrode and the a-IGZO channel is used to decrease the contact resistance of S/D and improve the electrical performance. Sequentially, in order to decrease the leakage current of IGZO TFT, the Schottky contact source would be used to provide a Schottky barrier height for resisting the carrier transport at off-state of device. In another aspect, we fabricated the ZrSiO gate dielectric and Ti-doped channel to improve the electrical performance and reliability of TFT. The best electrical performance of this dissertation is the use of co-sputtered Titanium doped indium gallium zinc oxide (Ti-IGZO) channel with Zr0.85Si0.15O2 gate dielectric. It is found that oxygen vacancies in Ti-IGZO channel is decreased after Ti atom incorporation and stability of the TFT could be considerably improved. It reveals that Ti-IGZO channel prepared at a power ratio of IGZO:TiO2=80 W:25 W with a PDA a shows the best device performance of I_on⁄I_off , the SS, and the ∆V_TH after 1000 s positive/negative gate-bias stress are of 1.65×10^8, 90 mV/dec, and 0.157 V/-0.093 V, respectively.
From the results mentioned above, the optimized engineering of source/drain contact and development of novel gate dielectric and channel layer have shown excellent electrical performance. In this thesis, the RDS can be decreased by insertion of buffer layer and advance the electrical performance. To improve the leakage performance of IGZO TFT, the IGZO SB-TFT with a Schottky source structure is fabricated and show the lowest leakage current at off-state. In addition, the novel channel and dielectric layer with low trap density are manufactured by co-sputtering technique. As the results, IGZO TFTs with the novel channel and dielectric layer show the excellent electrical and reliability performances. The S/D optimized engineering and development of novel gate dielectric and channel are very promising for application in system-on-panel (SoP) and organic light-emitting (OLED) display in the future.

Chapter 1
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Chapter 2
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Chapter 3
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Chapter 4
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Chapter 5
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Chapter 6
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Chapter 7
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