隨著科技日新月異的發展，為了獲得更好的效能，半導體元件不斷的微縮，在尺寸微縮後遇到的一大問題便是短通道效應變得更加嚴重，而超薄基體全空乏絕緣層上矽金氧半電晶體(UTBB FD-SOI)有良好的閘極控制力，是抑制短通道效應的一好選擇，並且在超越摩爾時代，5G以及物聯網是半導體領域裡大力發展的項目，5G需要的是低雜訊並且可以高頻操作，物聯網需要低功耗及操作速度快，這些正是超薄基體全空乏絕緣層上矽所具有的優點。
論文中我們使用Sentaurus TCAD模擬出具有超薄基體以及氧化層的橫向擴散金氧半場效應電晶體(LDMOS)作為系統單晶片(SOC)中的高壓輸入-輸出元件(I/O Device).首先觀察在不同漂移區濃度及漂移區長度時的崩潰電壓與導通電阻，可以得知漂移區濃度所造成電場的不同進而影響崩潰電壓。此外我們搭配核心元件(Core Device)在高臨界電壓，標準臨界電壓，低臨界電壓時的三種背閘極偏壓，來呈現在三種偏壓狀態下，輸入輸出元件的崩潰電壓，特徵導通電阻的變化。深入探討其中的原因後，我們發現背閘極偏壓在LDMOS中具有降低表面電場的功效而調變漂移區的峰值電場，不過也會提升次高峰值的電場，除此之外背閘極偏壓也會調變漂移區的電阻，因此整個高壓輸入輸出元件的表現也會因此而改變。

With the rapid development of technology, the semiconductor devices continue to scale in order to obtain better performance. We have encountered a major problem after shrinking the size as the short channel effects become more serious. The Ultra-Thin Body and Box FD-SOI MOSFET (UTBB FD-SOI) has good electrostatic gate control over the channel and is a good choice to suppress short channel effects. In the era of More than Moore, 5G and the Internet of Things are vigorously developed projects in the semiconductor field. 5G needs low noise and high frequency operation. The Internet of Things requires low power consumption and high operation speed. These are exactly the advantages of FD-SOI.
In this thesis, we use Technology Computer-Aided Design (TCAD) to study the laterally diffused MOSFET (LDMOS) with an ultra-thin body and oxide layer as the high-voltage input-output device (I/O device). First, LDMOS with different drift region lengths and doping concentrations are simulated, and we can understand how the electric field caused by the concentration of the drift region is different, which affects the breakdown voltage. Furthermore, three distinct back-gate biases used in core devices corresponding to three off-state leakage current criteria for high threshold voltage, standard threshold voltage, and low threshold voltage, respectively, are applied to the I/O cell. The use of back-gate bias can reduce the highest peak electric field and also increase the second highest peak electric field in the drift region. Furthermore, the series resistances in the drift region are also modulated by the back-gate bias. Therefore, the performance is changed due to the back-gate bias.

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