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研究生： 謝坤諺
Hsieh, Kun-Yen
論文名稱： 一個十位元每秒取樣二十萬次0.7微瓦的逐漸趨近式類比數位轉換器
A 10-bit 200-kS/s 0.7-µW Successive-Approximation Analog-to-Digital Converter
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系碩士在職專班
Department of Electrical Engineering (on the job class)
論文出版年： 2012
畢業學年度： 100
語文別： 中文
論文頁數： 70
中文關鍵詞： 類比至數位轉換器 、逐漸趨近式 、逐漸趨近式類比至數位轉換器
外文關鍵詞： ADC, SAR ADC, SAR, analog-to-digital converter, successive approximation, low-power
相關次數： 點閱：109  下載：10 
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    • 本論文主要實現一個十位元每秒取樣二十萬次的逐漸趨近式類比數位轉換器。為了降低功率消耗，在此論文中，提出跳躍式視窗(bypass window)的電路技巧來有效降低數位控制電路，比較器與電容陣列的能量消耗。除此之外，為了降低DAC單位電容與電容陣列的面積，我們採用新的電容架構，此架構電容可以減少寄生電阻、電容及對地雜訊。
    本論文中的類比數位轉換器是使用TSMC 0.18-µm 1P6M互補金氧半製程下線驗證。核心電路的面積為160 µm x 320 µm。量測結果顯示在0.6-V的電壓及200kS/s的取樣頻率下，可達到有效位元數為9.2位元，消耗功率為0.73 µW，而FOM 是6.12fJ/conversion-step。

    This thesis presents the design of a 10-bit 200-kS/s successive-approximation analog-to-digital converter (ADC). A bypass window-technique is proposed to reduce the power consumption of the digital control circuits, comparator, and capacitor array significantly. Additionally, a new capacitor, which has a very small feature size, is proposed to reduce the parasitic resistance and capacitance at the top plate for decreasing ground noise.
    The ADC was fabricated in TSMC 0.18-µm 1P6M CMOS process with the active area of 160 µm x 320 µm. The measurement results show that the effective number of bits is 9.2 bits and the power consumption is 0.73 µW with a 0.6-V supply at 200kS/s, which consequently results in a figure-of-merit of 6.12fJ/conversion-step.

    目錄 圖目錄VIII 表目錄IX 第1章 序論1 1.1 研究動機1 1.2 論文組織架構4 第2章 類比數位轉換器基礎概念與架構5 2.1 類比數位轉換器基礎概念5 2.2 類比數位轉換器性能評估標準6 2.2.1 解析度(Resolution)7 2.2.2 準確度(Accuracy)7 2.2.3 位移誤差(Offset Error)8 2.2.4 增益誤差(Gain Error)8 2.2.5 非線性(Nonlinearity)9 2.2.6 信號雜訊比(Signal-to-Noise Ratio)11 2.2.7 信號雜訊失真比(Signal-to-Noise and Distortion Ratio) 12 2.2.8 有效位元(Effective Number of Bits)12 2.2.9 無諧波失真動態範圍(Spurious Free Dynamic Range)13 2.2.10 全諧波失真(Total Harmonic Distortion)13 2.2.11 品質因素(Figure-of-Merit)13 2.3 類比數位轉換器架構分類14 2.3.1 快閃式類比數位轉換器15 2.3.2 管線式類比數位轉換器16 2.3.3 逐漸趨近式類比數位轉換器17 2.4 類比數位轉換器各式架構總結18 第3章 逐漸趨近式類比數位轉換器電路設計19 3.1 逐漸趨近式演算法19 3.2 逐漸趨近式類比數位轉換器架構與操作20 3.2.1 以數位類比轉換器為基礎之逐漸趨近式演算法20 3.2.2 電荷調變式逐漸趨近式類比數位轉換器21 3.3 非同步時序電路技巧 25 3.4 電容切換能量程序27 3.4.1 電容切換能量分析27 3.4.2 傳統電容切換[21] 29 3.4.3 傳統式電容切換能量消耗34 3.4.4 單調式電容切換能量消耗[11] 35 3.4.5 分裂單調式切換能量消耗[24] 37 3.4.6 電容切換程序總結40 第4章 一個十位元每秒取樣二十萬次的逐漸趨近式類比數位轉換器42 4.1 研究動機 42 4.2 跳躍式視窗電路技巧(BYPASS WINDOW)43 4.3 逐漸趨近式類比數位轉換器架構與運作45 4.4 電容式數位類比轉換器之容忍機制48 4.5 電路實現 50 4.5.1 比較器設計50 4.5.2 電容串陣列51 4.5.3 取樣與保持電路53 4.5.4 數位邏輯控制電路55 4.6 電路佈局與量測儀器設置56 4.7 量測數據 59 4.8 效能規格比較63 第5章 結論65 5.1 結論65 參考文獻 67

    [1]H. C. Hong and G. M. Lee “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, pp. 2161-2168, Oc. 2007.
    [2]N. Verma and A. P. Chandrakasan, “A 25-µW 100-kS/s 12-bit ADC for Wireless Micro-Sensor Application,” in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 822-831.
    [3]D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
    [4]Y. K. Chang, C. S. Wang, and C. K. Wang, “A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Applications,” in IEEE ASSCC Dig. Tech. Papers, Nov. 2007, pp. 228-231.
    [5]W. Y.Pang, C. S. Wang, Y. K. Chang, N. K. Chou, and C. K. Wang, “A 10-bit 500-KS/s Low Power SAR ADC with Splitting Capacitor for Bio-Medical Applications,” in IEEE ASSCC Dig. Tech. Papers, Nov. 2009, pp. 149-152.
    [6]S. K. Lee, S. J. Park, Y. Suh, H. J. Park, and J. Y. Sim, “A 1.3-µW 0.6-V 8.7-ENOB Successive Approximation ADC in 0.18-µm CMOS,” in Symp. on VLSI Circuitsd Dig .Tech.Paper, Jun. 2009, pp. 242-243.
    [7]J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 1.5-V 1-µW successive approximation ADC,“ in IEEE J. Solid-State Circuits, vol. 38, pp. 1261-1265, Jul. 2003.
    [8]Gilbert Promitzer, “A 12-bit Low-Power Differential Switched Capacitor Non-calibrating Successive Approximation ADC with 1-MS/s, ” in IEEE J. Solid-State Circuit, vol. 36, pp.1138-1143, Jul. 2001.
    [9]C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92-mW 10-bit 50-MS/s SAR ADC in 0.13-µm CMOS process,” in Symp. on VLSI Circuits, Jun. 2009, pp. 236-237.
    [10]B. P. Ginsburg and A. P. Chandrakasan “A 500-MS/s 5-bit ADC in 65-nm CMOS,” in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, Jun.2006, pp. 174-175.
    [11]C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010.
    [12]Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U R. P. Martins and F. Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111-1121, Jun. 2010.
    [13]B. Razavi, Principles of Data Converter System Design, New York: Wiley, 1995.
    [14]D. Aksin, M. Al-Shyoukh and F. Maloberti, “Switch Bootstrapping for Precise Sampling Beyond Supply Voltage,” IEEE J. Solid-State Circuits, vol. 41, pp. 1938-1943, Aug. 2006.
    [15]B. P. Ginsburg and A. P. Chandrakasan, “Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver,” IEEE J. Solid-State Circuits, vol. 42, pp. 247-257, Feb. 2007.
    [16]M. V. Elzakker et al., “A 1.9-µW 4.4 fJ/conversion-step 10-bit 1-MS/s charge-redistribution ADC,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 244–245.
    [17]M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10-bit 50-MS/s 820-µW SAR ADC with on-chip Digital Calibration,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384-385.
    [18]S. K. Lee, S. J. Park, H. J. Park, and J. Y. Sim, “A 21- fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface,” IEEE J. Solid-State Circuits, vol. 46, pp. 651-659, Mar. 2011.
    [19]S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, pp. 2669-2680, Dec. 2006.
    [20]J. Yang, T. L. Naing and R. W. Brodersen, “A 1-GS/s 6-Bit 6.7-mW Successive Approximation ADC Using Asynchronous Processing,” IEEE J. Solid-State Circuits, vol. 45, pp. 1469-1478, Aug. 2010.
    [21]B. P. Ginsburg and A. P. Chandrakasan, “An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC,” in Proc. IEEE Int. Symp. Circuits and Systems, May 2005, pp. 184-187.
    [22]Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Applications,”in IEEE A-SSCC Dig. Tech. Papers, Nov. 2007, pp. 228-231.
    [23]M. Furuta, M. Nozawa, and T. Itakura, “A 0.06mm2 8.9-bit ENOB 40-MS/s Pipelined SAR ADC in 65-nm CMOS,”in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 382-283.
    [24]Y.-Z. Lin, C.-C. Liu, G.-Y. Huang, Y.-T. Shyu, and S.-J. Chang, “A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS,”in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, Jun. 2010, pp. 243-244.
    [25]W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, “A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications,”in IEEE A-SSCC Dig. Tech. Papers, Nov. 2009, pp. 149-152.
    [26]Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, K.-D. Kim, W.-Y. Lee, K.-T. Hong and J.-K. Kwon, “A 9.15-mW 0.22mm2 10-bit 204-MS/s Pipelined SAR ADC in 65-nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf., Sept. 2010,pp.1-4
    [27]C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, and C.-M. Huang, “A 1-V 11fJ/Conversion-Step 10-bit 10-MS/s Asynchronous SAR ADC in 0.18-μm CMOS,”in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, Jun. 2010, pp. 241-242.
    [28]C. Lillebrekke, C. Wulff and T. Ytterdal, “Bootstrapped switch in low-voltage digital 90-nm CMOS technology,”in Proc. 23rd NORCHIP Conference, Nov. 2005, pp. 234- 236.
    [29]A. M. Abo and P. R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
    [30]黃冠穎, “Design of energy efficient successive-approximation analog-to-digital converter” MS Thesis, National Cheng-Kung Univ., Taiwan, Jul. 2007.

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