由於人們對於數位通訊、多媒體與影像處理的需求量越來越大，電路的複雜度變得越來越複雜。另一方面隨著半導體製程的快速進步，單一晶片中每單位面積可放置的電晶體數目越來越多，這樣的現象使得單一晶片可以整合的子系統比以前更多，架構也變得越來越複雜，這樣的晶片我們稱之為系統單晶片(SoC)或系統晶片。然而，當晶片面積變得越來越大，功能越來越複雜，晶片內部子系統資料傳輸與溝通就會變得很重要，甚至會變成影響整個晶片效能的重要因素。於是，近年來開始有許多研究主題是研究晶片內部通訊的問題，其中最熱門的莫過於所謂的晶片網路(Network on Chip)。
在本篇論文中，我們將探討晶片網路的各種特性，與其相關設計議題，如網路拓樸、路徑安排、交換技術、封包傳送等等，並說明其硬體實作。我們的交換技術採用蟲洞交換，並且增加了虛擬通道的方法。網路介面亦有對應的資料緩衝區用以接收從交換器來的資料封包，進而達到快速資料傳送並降低資料傳輸延遲的目的。本論文所提出的電路，根據SYNOPSYS的Design Vision和TSMC’s 0.18μm的標準元件庫合成結果，運作速度可以到達 167 MHz。

During the 1990s, more and more processor cores and large reusable components have been integrated on a single silicon die‚ which has become known under the label System on Chip (SoC). SoC design provides integrated solutions to many applications such as computer systems, telecommunications, consumer electronics, multimedia, and so on. Thus, the communication between all the components in a chip is important. Most of the current communication architectures in SoC are based on dedicated wires or buses. The problems of data delay, synchronization, noise and signal reliability in bus communication are far more serious. In order to ensure the validity of data transfer and communication in SoC, the packet-switched network which delivers message between communicating components is a potential solution. That kind of architecture is called Network-on-chip (NoC). It is a new communication architecture which helps to meet the challenge of designing a complex SoC.
In the thesis, we discuss the design issues of the NoC, the modules or components of Network Interface (NI), and the design and implementation of switch and NI in NoC. In order to obtain better efficiency, we have designed a NI with simple direct memory access. By using the extended-butterfly fat tree as the network topology and the techniques of wormhole switching and virtual channel for packet transmission, our design can achieve fast data transfer and lower latency. We used SYNOPSYS Design Vision to synthesize the design with TSMC’s 0.18μm cell library. Synthesis result shows that the proposed design yields a processing rate of about 167 MHz.

[1] AMBA Bus specification, http://www.arm.com, 1999.
[2] Wishbone Service Center, http://www.silicore.net/wishbone.htm, 2004.
[3] CoreConnect Specification, http://www3.ibm.com/chips/products/coreconnect/, 1999.
[4] Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, and Wen-Kai Tsai, “Fast Fair Crossbar Scheduler for On-chip Router,” Circuits and Systems, pp. 385-388, May, 2007.
[5] Shih-Hsun Hsu, Yu-Xuan Lin and Jer-Min Jou, “Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs,” Asian Solid-State Circuits Conference (A-SSCC) 2006, 13-15, Nov., 2006.
[6] J. Liu, L. R. Zheng and H. Tenhunen, "A Guaranteed-Throughput Switch for Network-on-Chip," Proceedings of International Symposium on System-on-Chip, Nov. 2003.
[7] P. T. Wolkotte, Gerard J. M. Smit, Gerard K. Rauwerda, L. T. Smit, "An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip," 19th IEEE International Parallel and Distributed Processing Symposium, 2005.
[8] J. Kim, D. Park, T. Theocharides and N. Vijaykrishmam, "A Low Latency Router Supporting Adaptivity for On-Chip Interconnects," DAC , 13-17 , June, 2005.
[9] John L Hennessy, David A. Patterson, “Computer Architecture, A Quantitative Approach 3rd edition”, MORGAN KAUFMANN, 2002
[10] Lai, C. L. Lei, and H. H. Chiou, "A False-Sharing Free Distributed Shared Memory Management Scheme," to appear in IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E83-D, No.4, 2000.
[11] S. -D. Wang, C. -S. Chi, and K. -C. Su, "EASY: A Dynamic Distributed Shared Memory System,"Proceedings of 1995 Workshop on Distributed System Technologies and Applications, Tainan, Taiwan, July 1995. (Proc., pp. 41-48).
[12] Wen-Yew Liang, Chun-Ta King and F. Lai, "Adsmith: An Object-Based Distributed Shared Memory System for Network of Workstations," IEICE Trans. on Information & Systems, Vol. E80-D, No. 9, pp. 899-908, September 1997.
[13] H.H.Wang and R.C.Chang (1994). A Distributed Shared Memory System with Self-Adjusting Coherent Scheme, Parallel Computing, Vol.20, No.7, pp. 1007-1025.
[14] Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich Weber, Anoop Gupta, John Hennessy, Mark Horowitz, Monica S. Lam, "The Stanford Dash Multiprocessor," Computer, vol. 25, no. 3, pp. 63-79, Mar., 1992.
[15] K. Li and P. Hudak. Memory coherence in shared virtual memory systems. In Proc. of the 5th Annual ACM Symp. on Principles of Distributed Computing (PODC'86),
[16] W.J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proc. Design Automation Conf. (DAC), pp. 683-689, 2001.
[17] P.P.Pande, C.Grecu, A.Ivanov, and R.Saleh, “Performance Evaluation and Design Trade-Offs,” IEEE TRANSACTIONS ON COMPUTERS, vol.54, no. 8, Aug., 2005.
[18] Hemayet Hossain, Md. Mostofa Akbar, and Md. Monirul Islam, “Extended-butterfly Fat Tree Interconnection (EFTI) Architecture for Network on Chip,” IEEE Pacrim Conference on Communications, Computers and Signal Processing (PACRIM) University of Victoria, Canada, Aug., 2005.
[19] William J. Dally, “Virtual Channel Flow Control,” IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, Mar., 1992.
[20] Samsung, http://www.samsung.com
[21] ARM, http://www.arm.com