本論文研究介電層的偶極極化效應對有機薄膜電晶體的電特性影響，實驗分為兩部分，實驗第一部分主要探討偶極對雙極性有機薄膜電晶體的電特性影響，第二部分聚焦於偶極對單極性有機薄膜電晶體的電特性影響。
第一部分以五苯環素 (Pentacene) 做為雙極性有機薄膜電晶體之主動層，探討介電層中加入具有鐵電性質的聚二氟乙烯 (Polyvinylidene fluoride，PVDF) 極化層後，偶極極化效應對元件電特性的影響，實驗結果指出，PVDF 極化層被聚甲基丙烯酸甲酯 (Polymethylmethacrylate，PMMA) 覆蓋之複合介電層，能提升元件在 N 型操作時的輸出電流並降低臨界電壓。當 PVDF 的偶極極化效應經電場極化達最大化後，電流增益的效果與載子遷移率可大幅提升，電子與電洞的載子遷移率達 2 cm2/Vs 以上，使元件在 N 型操作及 P 型操作下有更匹配的載子遷移率與輸出電流。雖然 PVDF 的偶極極化效應無法提升元件在 P 型操作時的輸出電流與載子遷移率，但導納分析及同步施加電場的方式 (in-situ) 量測拉曼光譜的結果顯示，PVDF 的偶極極化效應可使主動層經電場應力後，仍然可以維持良好的結構均勻性，也可降低主動層與介電層間的缺陷態密度，因此元件操作時有更好的穩定性。另外，PVDF 偶極電場可加速半導體層中電子電洞對的分離過程，使主動層與介電層間界面的缺陷鬆弛時間減少約一半。由 X-ray 繞射 (X-ray diffraction，XRD) 與原子力顯微鏡 (Atomic force microscope，AFM) 的觀測結果發現介電層表面粗糙度與半導體層結晶並非影響載子傳輸的主要因素，更加凸顯 PVDF 的偶極極化效應對元件電特性表現所造成的影響。
第二部分探討 PVDF 的偶極極化效應對以駢苯衍生物 (Perylene diimide derivative，PTCDI) 為主動層之單極性有機薄膜電晶體的電特性影響，實驗結果顯示，PVDF 的偶極極化效應雖然有助於載子通道提早形成，降低元件的臨界電壓，但載子受到偶極電場的束縛而降低了閘極的控制能力，也造成半導體與介電層界面有較大的缺陷態密度且載子受缺陷態侷限的時間較長。我們也發現元件特性受 PVDF 的偶極極化效應影響程度與 PTCDI 的碳鏈長度有關，PTCDI 的碳鏈長度增加會屏蔽 PVDF 的偶極極化效應。

This study investigated the electrical characteristics of organic field-effect transistors (OFETs) influenced by the gate dielectric polarization effect (dipole effect). In the first part, pentacene-based ambipolar OFETs with a polyvinylidene fluoride (PVDF) polarization layer were explored. The dipole effect significantly increased the drain current and reduced the threshold voltage of the devices because of the internal electric field. An external electric field maximized the dipole effect and balanced the saturated mobility in both the electron and the hole. The saturated mobility in both electron and hole was over 2 cm2/Vs. The dipole effect reduced the interfacial trap density (Dit) and the trap/de-trap time (τit) on the dielectric/semiconductor interface and enhanced the stability of the devices with PVDF polarization layers. In the second part, perylene diimide derivative (PTCDI) -based unipolar OFETs with PVDF polarization layers were explored. Although the dipole effect contributed to the reduction of the threshold voltage, it decreased the gate control ability and increased the subthreshold swing of the devices. The carriers were bound by the dipole field, resulting in a large Dit and τit on the dielectric/semiconductor interface.

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