受到霧氣等不佳氣候條件影響，很容易使影像畫面受損，其他有霧的氣候會使畫面能見度降低，讓畫面內的物體模糊不清，影響後續的數位影像應用，例如：監視系統或行車紀錄器等，在有霧的情況下，造成擷取到的影像可能被霧氣遮蓋，無法得到完整且清晰的影像資訊，造成後續影像分析、應用上的困難。因此，如何對有霧影像進行有效的還原處理，一直是許多學者關心的議題。綜觀目前影像除霧相關的期刊論文，大多利用較複雜的演算法處理，無法滿足即時影像的應用。因此本論文提出一個複雜度低且適合以VLSI硬體電路實現的除霧演算法，將所拍攝的有霧影像，有效且即時的還原成較清晰的影像。本論文所提出的適應性除霧演算法，有三大特點：1)利用暗原色先驗統計(dark channel prior)技術來估計大氣光強度，再利用得到的大氣光強度計算，分別計算分割亮暗部的閥值(threshold)和適當的區域大氣光值。2)利用邊緣偵測來偵測物件的邊緣並減低光暈效應。3)同時計算大氣光值及還原無霧影像，藉此提高處理對於連續影像或視訊的除霧速度。實驗結果證明，本論文提出的方法比其他參考文獻能夠更有效的去除影像的霧氣，得出更高品質的畫面。針對所提出的除霧演算法，設計了一個高效能的六級管線化VLSI硬體架構，並使用Verilog硬體描述語言來實現。根據Synopsys Design Vision 搭配TSMC 130nm標準原件庫的合成結果，此電路需要的邏輯閘數為18.6K，工作時脈為200M Hz，其處理速度可滿足Full HD(1920X1080)每秒30張影像的格式需求，達到即時視訊畫面處理的效能。

In bad weather conditions such as fog or haze, the visibility of an image taken under such circumstances would be severely blurred. This is often the case for dashboard camera recording on freeways, recordings taken by security cameras in the morning if mountain areas, video evidence taken by coastguards, etc. Objects in this blurred images and recordings are oftentimes hard to distinguish, which makes it unsuitable to analyzing. Therefore, to find a method that recovers a clear image form a foggy one is a very important issue. Recently, various defogging techniques were proposed to process static images, but only a few of theses were suitable for VLSI design or real-time applications. Hence, the goal of this thesis is to propose an efficient video defogging method with low complexity that is suitable for VLSI circuit implementation.
The proposed method has three characteristics: First, estimating the global atmospheric light by dark channel prior, and computing the local atmospheric light according to visibility of patch. Second, using an edge detection to ease the halo effect. Third, calculating the atmospheric light and the recovered images at the same time, exploiting temporal dependency to increase the processing rate. The experiment results show, by comparing the recovered images of our method with other hardware implementation methods, that the former was more efficiently and delivered images at a higher quality.
The hardware architecture of the proposed design was implemented by Verilog and Synopsys Design Compiler was used to synthesis the design with the TSMC 130nm cell library. The synthesis result showed that the proposed design contains 18.6K gate counts. The design works with the processing rate of 200 Mpixels/s, which is fast enough to process Full HD resolution at 30 fps in real time.

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