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研究生：	董得龍 Tung, Teh-Lung
論文名稱：	具切換架構之兩通道TDES FPGA硬體引擎實現並應用於快閃記憶卡資料保護 FPGA Implementation of Two-Way, Switching Mode 128-bits TDES Hardware Engine and Applications to Data Protection of Flash Memory Card
指導教授：	廖德祿 Liao, Teh-Lu
學位類別：	碩士 Master
系所名稱：	工學院 - 工程科學系 Department of Engineering Science
論文出版年：	2009
畢業學年度：	99
語文別：	英文
論文頁數：	52
中文關鍵詞：	Triple DES 、加密、FPGA 、USB 、SD 、儲存
外文關鍵詞：	Triple DES, Encryption, FPGA, USB, SD, Storage
相關次數：	點閱：65 下載：4
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近十年來，隨著半導體技術的長足進步，高容量且體積小的隨身裝置亦不斷地被研發出來，個人隨身儲存裝置也因此越來越普及。此外，資料數位化亦使數位內容更加廣泛地被使用。但日常生活中，常因為各種原因，導致儲存裝置中的資料為他人所竊取或破壞。而被竊取的資料中，有許多資料是屬於個人隱私或者是企業機密。而絕大部分被竊取的原因是資料本身並未經過謹慎的加密處理，使得竊取者可以任意使用。因此，資料安全成為一個重要的研究方向。在本論文中，採用了高保密性的Triple-DES做為數位化個人資料的安全保密方式，並以FPGA設計論文中所提出的四種架構。最後，以實際的個人電腦與儲存裝置(SD card)完成加密/解密的功能驗證，並對論文中所提出的Triple-DES加/解密架構進行效能分析。

In recent decade, due to the great progress of semiconductor industry, storage devices have become the most universal device. Since the data was widespread by digitization. Using digital data is a convenient and simple propagation method. However, digital data is also easy to be destroyed or stolen. For protecting personal data in commercial business, the data encrypt technology has become an important issue. In this paper, a modified Triple-DES structure is proposed and designed on FPGA. The proposed structure is verified and guaranteed with PC, storage device and card reader.

CHAPTER 1  INTRODUCTION	1
1 Motivation and Goal	1
2 Thesis Content	2
CHAPTER 2  BASIC THEORY	3
1 USB Interface	3
1.1 History and Brief	3
1.2 Transfer Architecture	4
1.3 Transfer Types	5
2 SD card standard	6
3 Triple-DES Algorithm	8
3.1 History	8
3.2 DES Algorithm	9
3.3 The f-Function	14
3.4 Sub-Key Generate Schedule	17
3.5 Triple-DES	20
CHAPTER 3  SYSTEM ARCHITECTURE	22
1 System Architecture Overview	22
2 Firmware Coding on MCU	23
3 Triple-DES Hardware Design and Implementation on FPGA	25
3.1 Pin Assignment	26
3.2 Block Diagram of Triple-DES	27
3.3 DES Implement	28
3.4 Triple-DES Module Timing Diagram	31
4 A Two-Way, Switching Mode 128-bits TDES Hardware Implementation	32
4.1 Three-Stage Pipeline Triple-DES Module	32
4.2 Two-Way Processing Triple-DES Module	34
4.3 Switch Mode Triple-DES Module	35
CHAPTER 4  VERIFICATION AND COMPARISON	39
1 Test Platform	39
2 Verification	41
3 Performance Analysis and Comparison	43
CHAPTER 5  CONCLUSION	47
Reference	48
APPENDIX	50
                                    

[1] NIST, “Data Encryption Standard”, FIPS Pub 46-7, 1999.
[2] NIST, “Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher”, SP 800-67 Version 1.1, Revised 19 May 2008.
[3] 白宗堯, “IP-based design and chip implementation of the AES coprocessor with configurable parameter”, 國立交通大學碩士論文, July 2006.
[4] P. Hämäläinen, M. Hännikäinen, T. Hämäläinen, and J. Saarinen, “Configurable hardware implementation of Triple-Des Encryption Algorithm for wireless local area network”, Tampere University of Technology, 2001.
[5] S. Guilley, P. Hoogvorst and R. Pacalet, “A fast pipelined multi-mode DES architecture operating in IP representation”, VLSI journal 40 (2007) 479–489.
[6] R. C.-W. Phan and M. U. Siddiqi, “A Framework for Describing Block Cipher Cryptanalysis”, IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 11, NOVEMBER 2006.
[7] H. M. Heys, “Analysis of the statistical cipher feedback mode of block ciphers”, IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 1, JANUARY 2003.
[8] E. W. Smith and D. L. Dill, “Automatic Formal Verification of Block Cipher Implementations”, Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, Portland Oregon, 2008.
[9] L. Ali, N. A. M. Yunus, H. Jaafar, R. Wagiran and E. Low, “Implementation of triple data encryption algorithm using VHDL”, ICSE2004, Kuala Lumpur, Malaysia, 2004.
[10] 趙子羽, “Hardware Design and Implementation of Triple-DES and AES Algorithms”, 國立交通大學碩士論文, 2002.
[11] L. M. Hong and L. J. Qiang, “USB Key-Based Approach for Software Protection”, 2009 International Conference on Industrial Mechatronics and Automation.
[12] Xilinx, “Spartan-3 Generation FPGA User Guide”, v1.4, June 2008.
[13] USB IF, “Universal Serial Bus Specification”, Reversion 2.0, 2000.
[14] SD Group, “SD Specifications Part 1: Physical Layer Simplified Specification”, Version 2.00, 25 September 2006.
[15] Cypress Semiconductor, “EZ-USB FX2 Technical Reference Manual”, Version 2.2, 2001

校內：2014-08-10公開
校外：2014-08-10公開

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