隨著摩爾定律的推進，元件必需微縮以達到更高的堆疊密度、更快的運作速度以及更節省能源。但在微縮的過程中遇到了諸多問題例如多晶矽的摻雜硼原子因熱處理穿過二氧化矽介電層進入通道影響電性表現、二氧化矽的厚度太薄無法有效抵擋直接穿遂的漏電流造成待機時能源損耗，且當二氧化矽的厚度小至某個程度時，多晶矽的空乏區將會產生明顯作用降低整體電容。為克服以上問題，多晶矽閘極與二氧化矽介電層需以金屬閘極與高介電常數材料取代之。本研究主要探討鎢-矽薄膜(W1-xSix)閘極電極中矽含量的改變對其功函數的影響。實驗使用共濺鍍法，製作W1-xSix薄膜，觀察薄膜的材料性質、電性表現及功函數隨矽含量增加的改變情況，並討論功函數、電表現性與材料性質之間的關係。本實驗分成二部份：
第一部份研究中，將W1-xSix薄膜製備在二氧化矽上，觀察W1-xSix薄膜本身的特性(第4章到第6章)。第4章重點在於研究W1-xSix薄膜的材料特性，觀察矽含量對於W1-xSix薄膜元素比例、結晶結構、化學鍵結性質及電阻率的影響。第5章的實驗研究當矽含量較低(Si < 14 atomic%)，鎢仍維持金屬相且矽原子仍以雜質原子的型式存在於鎢金屬中時，材料性質與電性表現之間的關聯性。吾人利用鎢靶(W)與矽靶(Si)共濺鍍的方法，將W0.90Si0.10 與 W0.86Si0.14薄膜沈積在SiO2/Si基板上，製作成金屬-氧化物-半導體(Metal-Oxide-Semiconductor, MOS)電容器；在薄膜沈積完成後，試片將於700 oC的氮氣(N2)中進行熱處理。從低掠角X光繞射的結果中發現，在W1-xSix薄膜中只有body-centered-cubic-W (bcc-W)及/或β-W兩相被觀察到，並無矽化物的相存在，然而鎢的晶格常數隨著矽含量的增加而增加。初鍍W0.90Si0.10與W0.86Si0.14薄膜的功函數分別為4.57 eV及4.47 eV，在經過700 oC熱處理後，其功函數改變為4.52 eV及4.38 eV。接著在第6章，進一步提高W1-xSix薄膜中的矽含量，若將W1-xSix薄膜中的矽含量提高至介於30-74 atomic %時，當試片在真空環境底下經過900 oC熱處理後，則可以在薄膜中觀察到矽化鎢(Tungsten silicide)的化合物結晶相出現；在幾乎為計量比的情況下，900 oC 熱處理後的W0.64Si0.36與W0.31Si0.69薄膜會形成W5Si3與WSi2相，而矽含量位於此兩薄膜中間的W0.44Si0.56薄膜則表現出W5Si3與WSi2兩相混合的結構；對於鎢含量較多的W0.70Si0.30薄膜而言，則形成W5Si3相加上微量的bcc-W；但另一方面而言，對於矽含量更高的W0.26Si0.74薄膜而言，則幾乎與W0.31Si0.69薄膜一樣，只表現出WSi2相。而對於經過900 oC 熱處理後的W0.70Si0.30，W0.64Si0.36，W0.44Si0.56，W0.31Si0.69與W0.26Si0.74薄膜，其功函數分別為4.34，4.31，4.61，4.76與4.72 eV。
本實驗的第二部份(第7章)則將W1-xSix薄膜製備在HfO2上，觀察W1-xSix/HfO2疊層結構在經過高溫熱處理後其界面特性與電性質的表現，並研究其關連性。在本章中，仍然是利用共濺鍍法，將W0.64Si0.36與W0.31Si0.69薄膜沈積在HfO2高介電常數介電層上製作成MOS電容器。在各層薄膜均沈積完成後，將試片進行900 oC的熱處理處理以使W0.64Si0.36與W0.31Si0.69轉變為矽化鎢結晶(分別為W5Si3與WSi2)結構。另外同時也製備了以W為電極的電容器作為對照。W0.64Si0.36與W0.31Si0.69在經過900 oC的熱處理處理後，在穿透式電子顯微鏡的影像中觀察到一層非晶態，類似二氧化矽(SiO2-like)的中界層在W1-xSix與HfO2之間形成，然而，其中的氧化層電荷(Oxide charges)及界面態(Interface states)在經過熱處理後呈現減少的趨勢。初鍍的W，W0.64Si0.36與W0.31Si0.69分別表現出功函數4.55，4.59與4.63 eV；在經過900 oC熱處理後，其功函數轉變為4.6，4.4與4.74 eV。在W的系統，不論是初製備或是經熱處理的試片，均表現出類似的功函數，推測是為費米能階釘札(Fermi level pining)的現象；在W0.64Si0.36與W0.31Si0.69中，在經過900 oC熱處理後，費米能階釘札的現象解除了，但W系統中仍有費米能階釘札的現象。推測此一費米能階釘札解除的現象是因為類二氧化矽的中界層在HfO2介電層與W1-xSix電極之間形成所造成，且同時也造成了等效氧化層厚度(Equivalent oxide thickness, EOT)的增加。最後吾人發現，在W0.31Si0.69與HfO2之間插入一層2 nm的WNx，除了可以抑制EOT的增加外，W0.31Si0.69仍可以主導功函數的表現。

To follow Moore』s Law, the device should be shrinkaged to reach higher device density, faster operation speed and lower power comsuption. However, many problems are encountered while scaling. For exemple, the SiO2 is too thin to avoide the the penetration of dopant boron from poly-Si after annealing and the high leakage current. In addition, the influence of depletion of poly-Si gate on the total gate capacitance becomes appearent. To overcome these problems, the poly-Si gate and SiO2 dielectric should be replaced by metal gate electrodes and high-k dielectrics.
In this study, the material characteristics, work functions and electric properties of W1-xSix film as gate electrode with various Si concentrations fabricated by co-sputtering are investigated. The correlation between material characteristics, work function and electric properties are discussed. This study includes two parts.
In the first part (Chapter 4 through 6), W1-xSix films are deposited onto SiO2 to examine the material properties of W1-xSix film itself. In Chapter 4, the influences of Si concentration on lattice, chemical bonding and resistivity of W1-xSix are studied. In Chapter 5, W1-xSix with the Si concentration lower than 14 at.% (in which, the W1-xSix still remains in tungsten crystalline) are selected to measure its electric properties and work function. W0.90Si0.10 and W0.86Si0.14 films are deposited on SiO2/Si substrates by co-sputtering from W and Si targets to form metal-oxide-semiconductor (MOS) capacitors. After deposition, the samples are subject to a thermal anneal at 700 oC in flowing N2 ambient. Only body-centered-cubic-W (bcc-W) and/or β-W are present in the W1-xSix films and no tungsten silicide phase is found. However, the lattice constant of W matrix is changed due to adding Si and annealing treatment. Work functions of as-deposited W0.90Si0.10 and W0.86Si0.14 are 4.57 eV and 4.47 eV, respectively. After annealing at 700 oC, the work functions of W0.90Si0.10 and W0.86Si0.14 become 4.52 eV and 4.38 eV, respectively. The connection between the work functions and material characteristics of W1-xSix is discussed.
In Chapter 6, the silicon concentration of W1-xSix is rised to 30-74 at.%. W1-xSix with continuous increase in Si content ranging from 30 to 74 at.%. The films are deposited on SiO2/Si substrates by co-sputtering from W and Si targets as well. After deposition, the samples are subject to a thermal annealing at 900 oC to form crystalline silicide phases. With their almost stoichiometric compositions, 900 oC-annealed W0.64Si0.36 and W0.31Si0.69 exhibit W5Si3 and WSi2 phases, respectively, while W0.44Si0.56 displays mixed phases of W5Si3 and WSi2. With excess in W, W0.70Si0.30 film exhibits W5Si3 phase with a trace of bcc-W. On the other hand, W0.26Si0.74 containing excess in Si shows WSi2 phase of similar crystallinity to that of W0.31Si0.69. Work functions of 900 oC-annealed W0.70Si0.30, W0.64Si0.36, W0.44Si0.56, W0.31Si0.69, and W0.26Si0.74 are extracted from the plot of flat-band voltage vs. SiO2 thickness of the related MOS capacitors and the values are 4.34, 4.31, 4.61, 4.76, and 4.72 eV, respectively. It is deduced that work function of W1-xSix is mainly related with the phases. Their connection is discussed.
In the second part (Chapter 7), W0.64Si0.36 and W0.31Si0.69 films are deposited onto HfO2/SiO2 by co-sputtering from W and Si targets to fabricate the MOS capacitors. After deposition, the samples are subject to a thermal annealing at 900 oC to form crystalline tungsten silicide phases. The MOS capacitor with W gate electrode is also prepared for comparison. An amorphous SiO2-like interlayer is observed from high-resolution transmission electron microscope between tungsten silicides and HfO2 after annealing at 900 oC. However, oxide charges and interface states decrease after annealing at 900 oC. The work function of as-deposited W, W0.64Si0.36, and W0.31Si0.69 are 4.55, 4.59, 4.63 eV, respectively. After annealing at 900 oC, the work functions become 4.6, 4.4, and 4.74 eV, respectively. The similar work function values of as-fabricated samples are indicative of Fermi level pinning. The pinning of Fermi level for W1-xSix gate electrodes is released after annealing at 900 oC while the work function of 900 oC-annealed W is still pinned at 4.6 eV. It is deduced that the elimination of Fermi level pinning effect of W1-xSix electrodes on HfO2 is mainly related to the formation of SiO2-like interlayer. Finally, a WNx layer with 2 nm in thickness is inserted between W0.31Si0.69 and HfO2. It is found that the thin WNx efficiently suppress the formation of SiO2-like interlayer and the W0.31Si0.69 still can dominate the work function.

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