由於費米能階釘扎效應(Fermi-level Pinning Effect)，在半導體與金屬介面處，照成有效金屬的功函數幾乎與理論能階位置無關。並構成很高的蕭特基能障 因而 提 高 歐姆接觸電阻及妨礙元件的電子與電洞的傳輸。這個釘扎效應可以是metal-induced gap states(MIGS)或因為金屬與矽，鍺，三五族等半導體的接面中有許多的表面缺陷(如斷裂鍵)或電偶極而形成。
在本論文中，我們藉由插入超薄絕緣層或摻雜金屬在金屬與矽基板中，詳細實驗研究改善費米能階釘扎效應與降低蕭特基能障。並選用製程簡單與低成本的室溫液相沉積法(RLD)來實現摻雜金屬與沉積薄膜。這是一種非傳統退火方式但可達極低接面的片電阻與接觸電阻的改善歐姆接觸方法。
因為矽的低成本，無論現在或未來在互補式電晶體中皆是最佳的通道材料選擇。甚至超越7奈米節點技術，也都可以在矽材料之元件中實現。故吾人選擇在矽基板上成長介電材料。並利用線性與對數電流密度圖與時間改變來觀察介電材料的不同厚度。吾人相信利用此種非退火的方式來達到接面非常低的源極/汲極片電阻與接觸電阻將是未來CMOS的非常重要技術。
本論文中針對這項技術作系統化研究，我們發現這些接觸電阻與薄膜厚度或摻雜金屬不同有很強的關係，表示在矽的表面的介面狀態缺陷，在費米能階釘扎效應中扮演很重要的角色。

Owing to Fermi level pinning (FLP), change of effective metal work functions on metal/semiconductor contacts becomes almost unavailable, and thus leading to a high effective Schottky Barrier Height (SBH) for electrons and holes transport. The origins of this pinning effect have been ascribed to either metal induced gap states or surface states arise from the native defects at the metal / Si, Ge or III-V surface, such as dangling bonds or dipole.
On the other hand, silicon (Si) is of still the best candidate for the channel material in now and near future complementary metal-oxide-semiconductor (CMOS) devices following the Moore's Law, even beyond 7nm node technology. In the limiting scaled CMOS devices, a nonalloyed source/drain (S/D) junction with very low sheet and contact resistances should be overcame.
In this work, we present a detailed experimental study of Fermi level deepening, Schottky barrier height reduction to Si and contact resistivity reduction using an ultrathin insulators or doped metal between metal and Si. Besides, a simple and room temperature liquid-phase deposition (RLD) is utilized to dope metal or deposit a low cost and high dielectric constant thin film, such as TiO2, ZrO2 and Al2O3. In order to research the impact of the dielectric choice on n-Si-based MIS contacts properties, current density (J-V) calculations were performed using the algorithm and linear lines displayed in variable thickness or times.
The studied results show that the depinning effect presents a strong dependence on the thin film thickness or doped metal, indicating the interface states due to the native defects on Si surface are likely to play the dominant role in FLP.

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