在現今的集成電路設計(Integrated Circuit Design) 中，電阻、電容以及電感被用於檢查電路運作效能。故為了方便電路設計，如何快速且精準地萃取這些參數是一
個重要議題。在這篇論文中，我們針對週期性結構電路中的子電路進行電阻研究。
首先，我們利用子電路中的洞數去分類所有可能發生的子電路；另一方面，我們研
究週期結構的電阻與子電路數量關連性。結果發現電阻與子電路數量呈現一個線性
關係。利用這個關係，我們可以建立起一組線性方程來外插進而得到逼近解，而我
們進行了些數值驗證，這個外插方法的相對誤差低於0.1% 且記算時間被大幅地縮
減。

The extraction problems for resistance, inductance and capacitance are big issues for
integrated-circuit (IC) design. These parameters are used in circuit simulation to check
the circuit’s functionality. Therefore, it is essential to obtain these parameters quickly
in IC design. In this thesis, we study the resistance extraction problem with periodic
patterns and investigate the resistance from the cell problem. First, we categorize
the cell problems by the number of holes which is also the macroscopic density in a
square/rectangle chip. Second, we study the cell problem and increase the problem
size rapidly for the cell problem to emulate the periodic patterns. We find that the
resistance approaches the resistance with periodic patterns linearly as the number of
cells increases. It enlightens us to create an extrapolation for the answer properly.
The numerical results show the relative error for the estimation is less than 0.1% and
the computation time is greatly decreased for the resistance extraction problem with
periodic patterns.

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