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研究生: 蔡家華
Tsai, Chia-Hua
論文名稱: 晶圓良率分析之Inline 量測資料分析
A framework to analyze in-line measurements for yield enhancement in wafer fabrication
指導教授: 鄭順林
Jeng, Shuen-Lin
學位類別: 碩士
Master
系所名稱: 管理學院 - 統計學系
Department of Statistics
論文出版年: 2017
畢業學年度: 105
語文別: 英文
論文頁數: 51
中文關鍵詞: 多階段製程迴歸樹統計製程管制良率分析Inline量測資料
外文關鍵詞: Multistage Manufacturing Process, Regression Tree, Statistical Process Control, Yield Analysis, Inline Measurement
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  • 晶圓片製造過程包含數百道製程,每一道製程都是由一連串生產步驟所組成。其中我們可以簡單地將生產過程分為以下幾個大項,分別是氧化、光刻技術、蝕刻技術、離子植入、拋光平坦化和金屬濺鍍。這些步驟會在晶圓片不同的光罩以及不同的參數設定下,重複循環進行著。部分生產步驟後面會緊接著量測站點以即時監控每道製程下,晶圓片的生產品質。但是,隨著半導體界邁入奈米製程,產品規格也變得越細緻且需要特別的量測器具加以輔助。即便每一道製程下,晶圓片都嚴格控管在管制界線內,但仍有部分晶圓片上的晶粒最後會呈現缺陷。因此,本篇論文旨在提出一套分析流程,利用統計製程管制想法以及迴歸樹模型,想要觀察哪些Inline量測值趨勢變化會導致高缺陷率的產生。這個分析流程結合兩種資料類型,分別是Inline量測資料和良率資料,合併兩種資料資訊可以更貼切地觀察晶圓片在每道製程下品質衰退的過程。分析結果中所有資料都經過適當的轉換以保護資料來源。

    Wafer fabrication contains hundreds of a series of process steps, including oxidation, photolithography, etching, ion implantation, planarization, metallization and so on. These steps are repeated over layers in a specific sequence with different masks and parameter setting. After a round of process steps, the inspection system follows and monitors whether the process is under control. However, as the semiconductor technology has stepped into the nano-fabrication process, the tolerance of specification has become even tighter. Although the in-line measurements of the shot, the exposed unit in photolithography process, on each layer is within the control limit, it is possible that some dies within the shot end up being defective. This study aims to propose a framework for analysing abnormal in-line measurements paths between processes within layer by introducing the idea of statistical process control and regression tree. The proposed framework, integrating two kinds of datasets, in-line measurements data and circuit probe test data, provides a better understanding of how the wafer degrades. The yield rates were modified to maintain confidentiality of the real data.

    Table of Contents 摘要i Abstract ii 誌謝iii Table of Contents iv List of Tables vi List of Figures vii Chapter 1. Introduction 1 1.1. Background and problem . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2. Literature review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.1. Process of semiconductor manufacturing . . . . . . . . . . . . . . . 3 1.2.2. Yield and the inline measurements . . . . . . . . . . . . . . . . . . 4 1.2.3. Statistical process control . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.4. Regression tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2. Data Introduction and Preprocessing 10 2.1. Data description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2. Data integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3. Wafer and shot levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4. Normalization for inline measurements . . . . . . . . . . . . . . . . . . . . 17 Chapter 3. Methodology 18 3.1. Statistical process control . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. Regression tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 4. Data Analysis 24 4.1. Wafer level analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1. Failure rate by all bincodes . . . . . . . . . . . . . . . . . . . . . . 24 4.1.2. Failure rate by top 1 bincode . . . . . . . . . . . . . . . . . . . . . 28 4.1.3. Failure rate by top 2 bincode . . . . . . . . . . . . . . . . . . . . . 30 4.2. Shot level analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.1. Failure rate by all bincodes . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2. Failure rate by top 1 bincode . . . . . . . . . . . . . . . . . . . . . 34 4.2.3. Failure rate by top 2 bincode . . . . . . . . . . . . . . . . . . . . . 36 4.3. Grouped inline measurements shot level analysis . . . . . . . . . . . . . . 38 4.3.1. Data preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.2. Failure rate by all bincodes with CD parameters . . . . . . . . . . . 39 Chapter 5. Conclusion 42 5.1. Major accomplishments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2. Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 References 44 Appendix A. Wafer level analysis 46 A.1. Failure rate by all bincodes . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A.2. Failure rate by top 1 bincode . . . . . . . . . . . . . . . . . . . . . . . . . 48 A.3. Failure rate by top 2 bincode . . . . . . . . . . . . . . . . . . . . . . . . . 50

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