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研究生： 林宜豊
Lin, Yi-Li
論文名稱： Versatile PC/FPGA Based Verification/Fast Prototyping Platform with Application to H.264/AVC I-frame Encoder
Versatile PC/FPGA Based Verification/Fast Prototyping Platform with Application to H.264/AVC I-frame Encoder
指導教授： 蘇文鈺
Su, Wen-Yu
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 中文
論文頁數： 60
中文關鍵詞： 驗證平台 、PCI 、系統級驗證 、軟硬體協同設計 、軟硬體協同驗證 、系統級設計
外文關鍵詞： Verification platform, IP verification, System level design/verification, Hardware/Software co-design/co-verification
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    • 　　現今SoC 設計儼然成為一大主流，尤其是在多媒體的應用，更是愈來愈重要。在晶片下單生產前，對IC 功能做徹底的驗證工作是必需的。大多數的IC設計公司會建造一以FPGA 為基礎的驗證平台來驗證。但設計及製造此一驗證平台所花費的代價並不低，並且目前輔助驗證的工具仍相當不完備。在本篇論文中，我們提出了一可重複使用於各類IC 設計的驗證平台，此平台包含軟體與硬體兩部份。硬體為一以FPGA 為主的電路驗證板，透過PCI Bus 與主機連接。軟體則在微軟的作業系統下開發，主要功能為傳送驗證資料給要被驗證的電路，以及將所有資料及電路處理後的資料做圖形化的呈現，方便使用者觀察驗證結果。我們也針對多媒體資料提供影像及聲音輸出，使用者可以即時觀看或聆聽經處理後的多媒體資料。藉由我們的系統，使用者能充份利用電腦裡的資源產生或取得大量的測試資料，像USB camera 等。亦能將大量的驗證結果儲存於其中，方便觀察電路是否正確運作。最後，我們實做了H.264/AVC I-Frame Encoder。
    H.264/AVC 是最新的視訊壓縮標準，其壓縮效率及品質比其他的標準更好。其中，H.264/AVC I-Frame 亦被證明其壓縮效率比JPEG 和JPEG2000 更佳。我們實作的H.264/AVC I-Frame Encoder 包含軟體及硬體，整個系統在我們的驗證平台上完成協同驗證。

    　　SOC design for multimedia applications becomes important these years. Before a chip is taped out, thorough verification on a FPGA based system is usually required. Most people tend to build a dedicated FPGA based evaluation board for a particular application or ASIC (Application Specific IC). The effort to build such a system is no less than that of designing the chip. Furthermore, the verification of the system relies　on tools such as logic analyzers which have quite a few limitations and are rather inconvenient to use. A versatile verification/fast prototyping platform consisting of a FPGA board and the associated system software is presented. The FPGA board is
    connected to the host computer through a PCI interface. The system software running within Microsoft Windows environment is developed so that all real-time data generated during simulation can be downloaded and displayed on the host computer. Particularly for multimedia applications, all processed data can be viewed or heard on the fly. User can take advantage of resources of computer to generate or gather test vectors for circuits. In addition, huge volumes of verification result can be stored in the computer for advanced comparison. Finally, we implemented a H.264/AVC I-Frame Encoder. H.264/AVC is quite a new video coding standard. Its compression efficiencies and qualities are better than others, including MPEG4. It is also proven that H.264/AVC I-Frame is better than JEPG and JPEG2000. Our H.264/AVC I-Frame Encoder System includes hardware and software. The system is co-verified in the proposed platform.

    摘要……………………………………………………………………………………I 誌謝…………………………………………………………………………………III 目錄…………………………………………………………………………………IV 圖目錄………………………………………………………………………………VI 前言……………………………………………………………………………………1 第一章研究動機…………………………………………………………………3 第二章IC 設計驗證流程及驗證工具簡介………………………………………6 第三章系統架構與功能…………………………………………………………10 3.1 系統架構………………………………………………………………….…11 3.2 PCI/FPGA 電路驗證板(PCI/FPGA-base Verification Board)…...…………11 3.3 系統軟體……………………………………………………………………14 3.4 驗證流程與電路驗證………………………………………………………17 3.4.1 驗證平台使用流程………………………………………………….17 3.4.2 電路驗證…………………………………………………………….19 第四章H.264/AVC I-frame Encoder…………………………………….………..23 4.1 H.264/AVC簡介…………………………………………………………….23 4.2 I-frame 壓縮方式解說……………………………………………………..27 4.2.1 Intra_4x4 預測方式………………………………………………...27 4.2.2 Intra_16x16 預測方式……………………………………………...31 4.2.3 Chroma 預測方式…………………………………………………..32 4.2.4 係數轉換(Transform)與量化(Quantization)……………………….34 4.2.4.1 針對誤差值所做的4x4 轉換與量化……………………….35 4.2.4.2 4x4 亮度DC 值轉換與量化…………………………………36 IV 4.2.4.3 2x2 彩度DC 值轉換與量化…………………………………37 4.3 H.264/AVC I-frame Encoder 系統設計……………………………………38 4.3.1 系統流程……………………………………………………………39 4.3.2 硬體架構與流程……………………………………………………40 4.3.3 I4MBPred 模組硬體架構與流程……………………………………42 4.3.4 I16MBPred 模組硬體架構與流程………………………………….44 4.3.5 ChromaPred 模組硬體架構與流程…………………………………46 4.3.6 Coeff 模組硬體架構與流程………………………………………...48 4.3.7 整合…………………………………………………………………50 第五章電路驗證……………………………………………………………………52 5.1 I16MBPred 模組驗證………………………………………………………52 5.2 Coeff 模組驗證……………………………………………………………..53 5.3 I16MBPred 與Coeff 整合模組驗證……………………………………….54 5.4 I4MBPred 與Coeff 整合模組驗證…………………………………………55 5.5 硬體電路整合驗證………………………………………………………...55 5.6 軟體與電路整合驗證…………….………………………………………..57 第六章結論與未來發展方向………...…………………………………………….59 參考文獻………………………………….………………………………………….60

    [1] http://www.altera.com
    [2] http://www.xlinx.com
    [3] 華新麗華報告書：數位生活與網際網路科技研發89.8~94.7
    [4] W. B. Huang, Y. J. Chang, Alvin W.Y. Su and Y. H. Kuo,"VLSI Design Of A
    DWT/Modified Efficient SPIHT Based Image Codec", IEEE ICICS-PCM 2003,
    Singapore, Dec., 2003
    [5] http://www.altera.com/products/devkits/altera/kit-apex_dev_kit.html
    [6] H.264: Advanced video coding for generic audiovisual services, ITU-T, May 2003
    [7] Till Halbach, Mathias Wien, “Concepts and Performance of next-generation Video
    Compression Standard”
    [8] Detlev Marpe, Valeri George, Hans L. Cycon, and Kai U. Barthel, “Performance
    evaluation of Motion-JPEG2000 in comparison with H.264/AVC operated in pure
    intra coding mode”.
    [9] http://bs.hhi.de/~suehring/tml/ H.264/AVC Software Coordination, JM7.3
    [10] Marpe, D.; Schwarz, H.; Wiegand, T.,“Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard”, Circuits and Systems for Video Technology, IEEE Transactions on, Volume: 13 , Issue: 7 , July 2003

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