本論文研製毫米功率結合技術之功率放大器及60-GHz CMOS次諧波射頻收發機前端毫米波晶片，採用TSMC CMOS 0.18-μm製程或90-nm製程。24-GHz CMOS變壓器耦合式功率放大器主要以4-way分散式主動變壓器(distributed active transformer, DAT)提升整體功率，並輔以共閘極偏壓處RF grounded的方式來克服製程頻率限制，改善頻帶內的增益特性。使用3-dB正交耦合器之60-GHz CMOS功率放大器運用縮小化耦合器作為功率結合/分波器，改善傳統架構面積過大而不利於電路整合之缺點，以低損耗與小面積之優勢提升放大器之輸出功率特性，量測結果顯示於60 GHz時，其增益為13.2 dB，飽和輸出功率為10.7 dBm，而PAEMAX為9 %，OP1dB則為9 dBm。60-GHz CMOS次諧波射頻收發機前端毫米波晶片為所設計的高增益功率放大器與之前已完成的次諧波接收機及收發開關晶片電路的整合，放大器的部分以電晶體疊接組態及串接三級實現高增益，藉以減輕前端電路的設計負擔。電路設計以Agilent ADS與Ansoft 3-D全波電磁模擬軟體HFSS進行模擬，量測部分則是採用on-wafer方式進行，根據欲量測特性之不同，相關量測方式亦有所調整。

This thesis presents the research on millimeter-wave (MMW) CMOS power amplifiers (PAs) using power combining techniques and the application of the PA in the integration of a 60-GHz fully-integrated CMOS sub-harmonic transceiver RF frond-end. The designed RFICs are implemented by standard TSMC 0.18-μm or 90-nm CMOS process. To increase the output power, the 4-way distributed active transformer is adopted in the 24-GHz CMOS PA. The gate of the cascode device is RF grounded with a large bypass capacitor to improve the limited gain of the CMOS process. For the design of the 60-GHz balanced PA, to improve the output power and provide an area-efficient solution, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme is employed as a low-insertion-loss power splitter/combiner. Measurement results show that the PA saturation power is close to 10.7 dBm with a power gain of 13.2 dB at 60 GHz. The peak PAE and the OP1dB are about 9 % and 9 dBm, respectively. Finally, a 60-GHz CMOS PA with a three-stage cascode configuration is designed to be integrated in a 60-GHz sub-harmonic transceiver RF front-end (with an integrated on-chip antenna and a balun filter). The high-gain performance of the PA can reduce the required input power level of the PA to alleviate the burden of the front-end circuit design. The Agilent ADS and Ansoft three-dimensional (3D) EM simulator HFSS are used for design simulation. The measured performances of the designed MMW CMOS RFICs are all performed by using the on-wafer measurement.

[1]J. A. Howarth, A. P. Lauterbach, M. L. J. Boers, L. M. Davis, A. Parker, J. Harrison, J. Rathmell, M. Batty, W. Cowley, C. Burnet, L. Hall, D. Abbott, and N. Weste, “60 GHz radios: enabling next-generation wireless applications,” in Proc. TENCON 2005 region 10, Nov. 2005, pp. 1–6.
[2]RF atmospheric absorption / ducting [Online]. Available: http://www.tscm.com/rf_absor.pdf
[3]IEEE 802.15 Working Group for WPAN. [Online]. Available: http://www.ieee802.org/15
[4]H.-C. Kuo, H.-L. Yue, Y.-W. Ou, C.-C. Lin, and H.-R. Chuang, “A 60-GHz CMOS sub-harmonic RF receiver with integrated on-chip artificial- magnetic-conductor Yagi-antenna and balun-bandpass-filter for very- short- range gigabit communications,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1681-1691, Apr. 2013.
[5]I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002.
[6]P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1054–1063, May 2008.
[7]A. M. Niknejad, and H. Hashemi, “mm-Wave Silicon Technology: 60 GHz and Beyond,” Springer Science, New York, 2008.
[8]Steve C. Cripps, “RF Power Amplifiers for Wireless Communications,” 2nd ed., Artech House, 2006.
[9]張盛富，張嘉展，“無線通訊射頻晶片模組設計－射頻晶片篇，” 全華科技，2008。
[10]B. Razavi, “RF Microelectronics,” 2nd ed., Prentice Hall, Inc., 1998.
[11]廖哲宏，應用於IEEE 802.11a WLAN之5.7 GHz CMOS 射頻接收機及功率放大器RFICs，成功大學電腦與通信工程研究所碩士論文，民國九十二年。
[12]D. M. Pozar, Microwave Engineering, 3rd ed., John Wiley and Sons, Inc., 2005.
[13]G. Gonzalez, Microwave Transistor Amplifiers, 2nd ed., Prentice Hall, Inc., 1997.
[14]C.-Y. Law, and A.-V. Pham, “A high-gain 60GHz power amplifier with 20dBm output power in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 426–427, 7-11 Feb. 2010.
[15]林育聖，60-GHz與26-/77-GHz雙頻帶CMOS被動元件及主動濾波器之研製，成功大學電腦與通信工程研究所碩士論文，民國九十八年。
[16]J.-H. Tsai, Y.-L. Lee, T.-W. Huang, C.-M. Yu, and John G. J. Chern, “A 90-nm CMOS broadband and miniature Q-band balanced medium power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1129–1132.
[17]Y.-S. Jiang, J.-H. Tsai, and H. Wang, “A W-band medium power amplifier in 90 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 12, pp. 818–820, Dec. 2008.
[18]呂知穎，毫米波CMOS低變化插入損耗相移器與非對稱型射頻收發開關之研製，成功大學電腦與通信工程研究所碩士論文，民國一百零一年。
[19]J. R. Long, “Monolithic transformer for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.
[20]葉景富，24-GHz CMOS射頻前端晶片及毫米波電路之研究設計，成功大學電腦與通信工程研究所碩士論文，民國九十八年。
[21]J. Chen, and A. M. Niknejad, “A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 432–433, Feb. 2011.
[22]K.-Y. Wang, T.-Y. Chang, C.-K. Wang, “A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 19–23, Feb. 2012.
[23]J.-F. Yeh, J.-H. Tsai, and T.-W. Huang, “A 60-GHz power amplifier design using dual-radial symmetric architecture in 90-nm low-power CMOS,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 3, pp. 1280–1290, Mar. 2013.
[24]A. Komijani, A. Natarajan, and A. Hajimiri, “A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1901–1908, Sep. 2005.
[25]J. -L. Kuo, Z. –M. Tsai and H. Wang, “A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-μm CMOS technology,” in Proc. IEEE European Microw. Conf., Oct. 2008, pp.2866-2869.
[26]Y. -N. Jen, J. -H. Tsai, C. -T. Peng and T.-W. Huang, “A 20 to 24 GHz +16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp.42-44, Jan. 2009.
[27]C. -C. Hung, J. -L. Kuo, K. -Y. Lin and H. Wang, “A 22.5-dB gain, 20.1-dBm output power K-band power amplifier in 0.18-μm CMOS,” in IEEE Radio Freq. Integr. Circuits Symp., pp. 557-560, May 2010.
[28]T.-Y. Chin, J.-C. Wu, S.-F. Chang, and C.-C. Chang, “Compact S-/Ka-band CMOS quadrature hybrids with high phase balance based on multilayer transformer over-coupling technique,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 3, pp. 708–715, Mar. 2009.
[29]T.-Y. Chin, J.-C. Wu, S.-F. Chang, and C.-C. Chang, “A V-Band 8 × 8 CMOS butler matrix MMIC,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 12, pp. 3538–3546, Mar. 2010.
[30]D.-W. Kang, K.-J. Koh, and G. M. Rebeiz, “A Ku-band 2-antenna 4-simultaneous beams SiGe BiCMOS phase array receiver,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 4, pp. 771-780, Apr. 2010.
[31]M. Bohsali and A. M. Niknejad, “Current combining 60 GHz CMOS power amplifiers,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2009, pp. 31–34.
[32]J.-W. Lai and A. Valdes-Garcia, “A 1 V 17.9 dBm 60 GHz power amplifier in standard 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2010, pp. 424–425.
[33]W.-L. Chan and J.-R. Long, “A 58–65 GHz neutralized CMOS power amplifier with PAE above 10% at 1-V supply,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 554-564, Mar. 2010.
[34]L. Chen, L. Li, and T.-J. Cui, “A 1V 18 dBm 60GHz power amplifier with 24dB gain in 65nm LP CMOS,” in IEEE Asia-Pacific Microw. Conf., Dec. 2012, pp. 13-15.
[35]W. Fei, H. Yu, Y. Shang, and K.-S. Yeo, “A 2-D distributed power combining by metamaterial-based zero phase shifter for 60-GHz power amplifier in 65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp. 505-516, Jan. 2013.
[36]C.-S. Kuo, H.-C. Kuo, H.-R. Chuang, C.-Y. Chen, and T.-H. Huang, “A high-isolation 60 GHz CMOS transmit/receive switch,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2011, pp. 1–4.
[37]J.-L. Kuo, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 50 to 70 GHz power amplifier using 90 nm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp. 45–47, Jan. 2009.
[38]Y.-N. Jen, J.-H. Tsai, T.-W. Huang, and H. Wang, “Design and analysis of a 55–71-GHz compact and broadband distributed active transformer power amplifier in 90-nm CMOS process,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 7, pp. 1637–1646, Jul. 2009.
[39]Y. Jin, M. A. T. Sanduleanu, and J. R. Long, “A wideband millimeter-wave power amplifier with 20 dB linear power gain and +8 dBm maximum saturated output power,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1553-1562, Jul. 2008.
[40]IEEE Std., 802.15.3c-2009, Oct. 2009. [Online]. Available:http://standards.ieee.org/getieee802/download/802.15.3c-2009.pdf
[41]A. Tomkins, R. A. Aroca, T. Yamamoto, S. T. Nicolson, Y. Doi, and Sorin P. Voinigescu, “A zero-IF 60 GHz 65 nm CMOS transceiver with direct BPSK modulation demonstrating up to 6 Gb/s data rates over a 2 m wireless link,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2085–2099, Aug. 2009.
[42]C. Marcu, D. Chowdhury, C. Thakkar, J.-D. Park, L.-K. Kong, M. Tabesh, Y. Wang, B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, E. Alon, and A. M. Niknejad, “90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3434–3447, Dec. 2009.
[43]Jri Lee, Y.-T. Chen, and Y.-L. Huang, “A low-power low-cost fully-integrated 60-GHz transceiver system with OOK modulation and on-board antenna assembly,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 264–275, Feb. 2010.
[44]H. Wang, M.-H. Hung, Y.-C. Yeh, and Jri Lee, “A 60-GHz FSK transceiver with automatically-calibrated demodulator in 90-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2010, pp. 95–96.
[45]K. Okada, N. Li, K. Matsushita, K. Bunsen, R. Murakami, A. Musa, T. Sato, H. Asada, N. Takayama, S. Ito, W. Chaivipas, R. M., T. Yamaguchi, Y. Takeuchi, H. Yamagishi, M. Noda, and A. Matsuzawa, “A 60-GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE802.15.3c,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2988–3004, Dec. 2011.
[46]A. Siligaris, O. Richard, B. Martineau, C. Mounet, F. Chaix, R. Ferragut, C. Dehos, J. Lanteri, L. Dussopt, S. D. Yamamoto, R. Pilard, P. Busson, A. Cathelin, D. Belot, and P. Vincent, “A 65-nm CMOS fully integrated transceiver module for 60-GHz wireless HD applications,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3005–3017, Dec. 2011.
[47]N. O. Sokal, and A. D. Sokal, “Class E–A new class of high-efficiency tuned single-ended switching power amplifiers,” IEEE J. Solid-State Circuits, vol. sc-10, no. 3, pp. 168–176, Jun. 1975.
[48]郭奇昕，毫米波CMOS高隔離度射頻收發開關及功率放大器之研製，成功大學電腦與通信工程研究所碩士論文，民國一百零一年。
[49]M. C. Yeh, Z. M. Tsai, R. C. Liu, K. Y. Lin, Y. T. Chang, and H. Wang, “Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 1, pp. 31–39, Jan. 2006.
[50]S. C. Chang, S. F. Chang, T. Y. Chih, and J. A. Tao, “An internally-matched high-isolation CMOS SPDT switch using leakage cancellation technique,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 7, pp. 525–527, July 2007.
[51]T. M. Hancock, and G. M. Rebeiz, “A 12-GHz SiGe phase shifter with integrated LNA,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 3, pp. 977–983, Mar. 2005.
[52]F. J. Huang, and K. K. O, “A 0.5-μm CMOS T/R switch for 900-MHz wireless applications,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 486–492, Mar. 2001.