| 研究生: |
劉育銘 Liu, Yu-Ming |
|---|---|
| 論文名稱: |
高電壓金氧半場效電晶體其特性與可靠度探討 Investigation of Device Characteristics and Reliability on High Voltage MOSFET |
| 指導教授: |
陳志方
Chen, Jone-Fang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2015 |
| 畢業學年度: | 103 |
| 語文別: | 英文 |
| 論文頁數: | 70 |
| 中文關鍵詞: | 高壓金氧半場效電晶體 、元件尺寸 、熱載子導致之退化 、閉態崩潰電壓 |
| 外文關鍵詞: | HVMOSFET, device dimension, hot-carrier-induced degradation, off-state breakdown |
| 相關次數: | 點閱:103 下載:9 |
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在本論文中,主要探討高壓金氧半場效電晶體(HV MOSFET)改變各種不同之尺寸參數時,對off-state breakdown與熱載子可靠度之影響,本篇論文中所使用之元件主要改變三個尺寸參數:Lgs(源極至閘極邊緣長度)、Lg(閘極長度)、Lds(汲極至閘極邊緣長度)。
先描述高壓金氧半場效電晶體之優點及應用,接著介紹貫穿崩潰(punch-through BD)、接面崩潰(junction BD)、GIDL(Gate-Induced-Drain- Leakage)、以及熱載子效應之基本原理。
之後介紹本論文中所使用的量測方法及條件,以及所使用之元件結構,也會呈現ID-VG及ID-VD基本之電特性。
本文研究之主要內容部分,首先探討改變尺寸參數對崩潰電壓之影響,透過量測及電腦輔助模擬(TCAD),可以發現改變Lg前後,主要有兩種不同之崩潰機制在主導,¬而改變Lgs並不影響崩潰電壓,且在不超過一定界線下,縮短Lgd並不會造成崩潰電壓之惡化。
經過需求之崩潰電壓篩選後,接著探討符合條件之元件的熱載子可靠度,從實驗結果得知不論縮短任一尺寸參數皆會造成熱載子可靠度之惡化,且其退化機制及位置皆相同,TCAD模擬結果也顯示Si/SiO2表面之衝擊離子化率(impact ionization rate)並無太大之差異,最後根據實驗結果分析改變哪一個尺寸參數能在不影響熱載子可靠度太多的情況下,帶來最大的效能改善。
關鍵字: 高壓金氧半場效電晶體,元件尺寸,熱載子導致之退化,閉態崩潰電壓。
In the thesis, hot-carrier-induced degradation and mechanism as well as the gate oxide integrity issue of high voltage metal-oxide–semiconductor field- effect transistors (HVMOS) with different layout parameters were investigated.
There were three kinds of parameter used in this thesis: Lgs (source-to-gate-edge), Lg (gate-length), and Lgd (drain-to-gate-edge).
First, the advantages and applications of HVMOS transistors were illustrated. Moreover, the basic theories of the punch-through breakdown, the junction breakdown, the gate-induced-drain-leakage (GIDL), and the hot carrier effect were also introduced.
The measurement setup device and the structure of our study were introduced. The measurement results of I-V characteristics including ID-VG & ID-VD was presented.
In the main part of content, the influence of varying the layout parameter on off-state breakdown was studied at first. By measurement and Technology on Computer Aided Design (TCAD), it could be observed that there were two different mechanisms dominating the breakdown before and after Lg is varied. The Lgs has a small influence on breakdown voltage. What’s more, shrinking Lgd under a certain limit would not worsen the off-state breakdown voltage.
After screening out the devices with qualified breakdown voltage, the hot carrier reliability of these devices were investigated. From the experiment results, the hot carrier reliability was deteriorated no matter which dimension parameter shrank. Besides, the hot carrier degradation mechanism and damaged position were also the same. The TCAD simulation indicated that impact ionization rate near Si/SiO2 had small difference in these devices. At last, according to the experiment results, shortening which parameter is the most effective way to increase the performance without affecting the hot carrier reliability too much.
[1] Innovative Power, IP - IPM4285 - 10-Output PMIC with Sequencing and I2C
[2] Crimsontt, http://www.crimsontt.com/IndustriesRetail.html
[3] Clive Maxfield (2007). Actel pioneering new markets for FPGAs in automobiles, EETimes
[4] Vaidyanathan Subramanian (2009) ,High Voltage MOSFET Technology, Models, and Applications, IBM
[5] Shrivastava, M., Jain, R., Baghini, M.S., Gossner, H., and Ramgopal Rao, V. (2010), “A Solution Toward the OFF-State Degradation in Drain-Extended MOS Device”,IEEE Transactions on Electron Devices, 57(2), pp. 448-457
[6] VanDerVoom, P., Gan, D., and Krusius, J.P. (2000),“CMOS shallow-trench-isolation to 50-nm channel widths”,IEEE Transactions on Electron Devices, 47(6), pp.1175 –1182
[7] Yamaguchi, Y, Iwamatsu, T., Joachim, H.-O., Oda, H., Inoue, Y., Nishimura, T., and Tsukamoto, K. (1994), “Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure”,IEEE Transactions on Electron Devices, 41(7), pp.1222-1226
[8] P. De., and P. K. Chakraborty (2004), “Effect of punch through on the microwave series resistance of n + np + Si IMPATT diodes around the X band”, Japanese Journal of Applied Physics (JJAP), 19(7), pp.859-863
[9] Shimohigashi, K., Barnes, J.J., and Dutton, R.W. (1978), “Characteristics of short channel MOSFETs in the punch-through current mode”, Electron Devices Meeting, International, 24, pp.66-69
[10] C. M., Hu (2010). Modern Semiconductor Devices for Integrated Circuits, Pearson.
[11] Hua Ye, and Haldar, P. (2008), “A MOS Gated Power Semiconductor Switch Using Band-to-Band Tunneling and Avalanche Injection Mechanism”, IEEE Trans. on Electron Devices, 55(6), pp1524-1528
[12] C. Hu (1979), “Optimum doping profile for minimum ohmic resistance and highbreakdown voltage,” IEEE Trans. Electron Devices, 26(3), pp.243-244
[13] Entner, R. (2007). Modeling and Simulation of Negative Bias Temperature Instability.
[14] Bill, W. (2008). Introduction to Physical Electronics, CNX.
[15] Donald, A. N. (2010). Semiconductor Physics and Devices: Basic Principles, Mc Graw Hill.
[16] Lim, K.Y., Yu, X., and Yeo, D. (2001), “A study on gate-induced junction breakdown”, Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on, October, pp.950-953
[17] Ja-Hao Chen, Shyh-Chyi Wong, and Yeong-Her Wang (2001), “An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET”, IEEE Trans. Electron Devices, 48(7), pp.1400-1405
[18] Chen, J.F., Chin-Rung Yan, Yin-Chia Lin, Jhen-Jhih Fan, Sheng-Fu Yang, and Wen-Chieh Shih (2011), “Analysis of GIDL-Induced off-State Breakdown in High-Voltage Depletion-Mode nMOSFETs”, IEEE Trans. Electron Devices, 58(6), pp.1608-1613
[19] Xiaobin Yuan, Jae-Eun Park, Jing Wang, Enhai Zhao, David C. Ahlgren,Terence Hook, Jun Yuan, Victor W. C. Chan, Huiling Shang,Chu-Hsin Liang, Richard Lindsay, Sungjoon Park, and Hyotae Choo (2008), “Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology”, 8(3), pp.501-507
[20] Li, Y. Q., C. A. T. Salama, M. Seufert, P. Schvan, and Mike King (1997), “Design and Characterization of Submicron BiCMOS Compatible High-Voltage NMOS and PMOS Devices,” IEEE Transactions on Electron Devices, 44(2), pp.331-338
[21] Zitouni, M., F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. PageÁs, and S. Merchant (1999), “A new lateral power MOSFET for smart power ICs: the ``LUDMOS concept'”, Microelectronics Journal , 30(6), pp. 551-561
[22] Shi, Y., N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer (2011), “Drift Design Impact on Quasi-Saturation & HCI for Scalable N-LDMOS”, IEEE International Symposium on Power Semiconductor Devices & IC's, San Diego, May, pp.215-218
[23] Klein, N., S. Levin, G. Fleishon, S. Levy, A. Eyal, and S. Shapira (2008), “Device design tradeoffs for 55v LDMOS driver embedded in 0.18 micronplatform”, IEEE 25th Convention of Electrical and Electronics Engineers in Israel, 2008. IEEEI 2008., Eilat, December, pp. 736-740
[24] Reggiani, S., S. Poli, E. Gnani, A. Gnudi, G. Baccarani, M. Denison, S. Pendharkar, R. Wise, and S. Seetharaman (2010), “Analysis of HCS in STI-based LDMOS transistors”, Reliability Physics Symposium(IRPS), 2010 IEEE International, Anaheim, May, pp. 881-886
[25] Tamma P. K. (2013), “Selecting P-channel MOSFET for Switching Applications”, Application Note AN-LV-11-2013-V1.0-EN-059, Infineon
[26] Aresu, S., R. Vollertsen, R. Rudolf, C. Schlünder, H. Reisinger and W. Gustin (2012), “Physical Understanding and Modelling of new Hot-Carrier Degradation Effect on PLDMOS Transistor”, Reliability Physics Symposium (IRPS), 2012 IEEE International, Anaheim, April, pp. XT.11.1-XT.11.6
[27] Bae, K., M. Jin, H. Lim, L. Hwang, D. Shin, J. Park, J. Heo, J. Lee, J. Do, I. Bae, C. Jeon, and J. Park (2011), “Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster”, Reliability Physics Symposium (IRPS), 2011 IEEE International, Monterey, April, pp. PL.1.1-PL.1.5
[28] Jie, B., Chim, W., M. Li, K. Lo (2011), “Analysis of the DCIV Peaks in Electrically Stressed pMOSFETs”, IEEE Trans. on Electron Devices, 48(5), 2011, pp. 913-920
[29] Chen, J., S. Chen, K. Wu, Shih, J., Wu, K. (2009), “Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors”, IEEE Trans. on Electron Devices, 56(11), pp. 2843-2847
[30] Wong, W., A. Icel (1995), “A comprehensive methodology and model for the characterization of hot-carrier induced MOS device degradation”, Devices, Circuits and Systems, 1995., Proceedings of the 1995 First IEEE International Caracas Conference, Caracas, December, pp. 183-187
[31] Hu, C. M., C. T. Simon, H. Fu-Chieh, P. K. ko, T. Y. Chan, and K. W. Terrill (1985), “Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement”, IEEE Journal of Solid-State Circuits, 20, pp. 295-305
[32] Agilent Technologies, B1500A semiconductor device analysis introduction
[33] Swin Super Solution & Service, http://www.3-s.com.tw/fengxi/front/bin/home.phtml
[34] SILVACO, http://www.silvaco.com/
[35] Ming-Jer Chen, Huan-Tsung Huang, Chin-Shan Hou, and Kuo-Nan Yang (1998), “Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's”, IEEE Trans. on Electron Devices, 19(4),pp. 134-136
[36] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu (1987), “The impact of gate-induced drain leakage current on MOSFET scaling”, IEDM Tech. Dig., pp.718 -721
[37] Chen, J.F., Chin-Rung Yan, Yin-Chia Lin, Jhen-Jhih Fan, Sheng-Fu Yang, and Wen-Chieh Shih (2011), “Analysis of GIDL-Induced off-State Breakdown in High-Voltage Depletion-Mode nMOSFETs”, IEEE Trans. on Electron Devices, 58(6),pp.1608-1613
[38] Shih-hui CHEN, JengGONG, Meng-chyi WU, Tsung-yi HUANG, Jei-feng HUANG, Ruey-hsin LIOU, Shun-liang HSU, Li-ling LEE and Hung-chun LEE (2003), “Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress”, Japanese Journal of Applied Physics (JJAP), 42(2),pp. 409-413
[39] Raychaudhuri, A. Deen, M.J., Kwan, W.S., and King, M.I.H (1996), “Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs”, IEEE Trans. on Electron Devices, 43(7),pp.1114-1122
[40] Chunlin Liang, Henry Gaw, and Peng Cheng (1992), “An Analytical Model for Self-Limiting Behavior of Hot-Carrier Degradation in 0.25-pm n-MOSFET's”, IEEE Trans. on Electron Devices, 13(11),pp.569-571