近年來數位相機已經廣泛地使用在影像擷取上。為了產生較精美的彩色數位影像，數位相機使用了許多影像處理的技術。在這些影像處理技術中，彩色濾波器矩陣內插法(interpolation)或稱解馬賽克法(demosaicking)可算是最重要的技術之ㄧ。以CCD的解析度而言，數位相機之影像品質乃決定於解馬賽克演算法的性能表現。綜觀目前之解馬賽克演算法可以分成兩類：較低成本的方式和較高成本的方式。後者會使用較複雜的方法來得到較好的影像品質，然而前者卻因為簡單性與較易以硬體實現的特質，會更適合在許多即時系統的應用上。當低成本實現是產品的主要考量時，如何發展出一個效果良好的低成本演算法與及硬體架構將會變得非常重要。本論文提出了一個低成本的解碼賽克演算法，藉由影像邊緣的特性和不同顏色之間的相關性來做內插處理，為了達到有效率的硬體實現，我們結合了硬體共用和管線化去完成一顆即時處理的晶片，我們電路架構的設計與實現是使用TSMC 0.35 標準元件庫來合成其電路。跟之前的硬體架構比較，我們可以達到較快的工作頻率以及較少的硬體成本。

Digital still cameras (DSC) have been widely used as image input devices nowadays. Before a color image is generated, a lot of color image processes must be performed. Among these color image processes, the Color Filter Array (CFA) interpolation or demosaicking process may be the most important process. In othe words, the image quality of a DSC depends highly on the performance of the demosaicking process. In general, the demosaicking methods can be classified into two categories: lower-complexity techniques and higher-complexity techniques. The complexity of the former is very low. The latter yields visually pleasing images by utilizing more sophisticated demosaicking methods. However, the former is more suitable for many real-time applications, due to its simplicity and easy implementation in the VLSI chip. An excellent lower-complexity interpolation method is still needed when low-cost VLSI implementation is necessary. In this thesis, a low-complexity interpolation scheme that exploits both spatial and inter-channel correlations is presented. To achieve the goal of area-efficient design, we adopt the resource sharing and pipelined scheduling approaches to develop the VLSI architecture for the proposed scheme. The VLSI architecture is designed with Verilog and implemented with TSMC 0.35 cell library. Compared with the previous design, our chip achieves less hardware cost and higher clock rate.

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