三態內容尋址記憶體(TCAM)可以儲存0、1和X，是一種被廣泛用在網路路由器中儲存路由表的記憶體。負偏壓不穩定效應(NBTI)和正偏壓不穩定效應(PBTI)會增加電晶體的臨界電壓而降低切換速度，成為電路設計中可靠度的主要議題。在這篇論文中，我們分析路由表的信號機率，發現許多記憶體單元將處在靜態壓迫，並造成嚴重的老化。因此，我們提出新的老化感知三態內容尋址記憶體來減緩偏壓不穩定效應的影響，包括使用位元翻轉(bit-flipping)及電源閘控(power gating)這兩種方法。同時，在經過位元翻轉後，為了維持功能的正確性，我們提出一個新的三態內容尋址記憶體設計。
實驗結果顯示，與原始架構相比位元翻轉分別可提升資料單元(data cell)16.84%的讀取靜態雜訊邊限(read SNM)和遮蔽單元(mask cell)29.94%的讀取靜態雜訊邊限，並且減少12.95%的搜尋時間衰退；而電源閘控可分別提升資料單元12.31%的讀取靜態雜訊邊限和遮蔽單元20.92%的讀取靜態雜訊邊限，及減少17.57%的搜尋時間衰退。若同時使用這兩種方法，將可分別提升資料單元17.74%的讀取靜態雜訊邊限和遮蔽單元 30.53%的讀取靜態雜訊邊限，並減少21.01%的搜尋時間衰退。

Ternary content addressable memory (TCAM), which can store 0, 1 and X in its cells, is widely used to store routing tables in network routers. Meanwhile, NBTI (Negative Bias Temperature Instability) and PBTI (Positive Biased Temperature Instability), which increase Vth and degrade transistor switching speed, have become major reliability challenges. In this paper, we analyze the signal probability of routing table, and the results show that many cells remain static stress and suffer significant BTI degradation. We propose two techniques, bit-flipping and power gating, to mitigate BTI effects. Meanwhile, in order to maintain the functionality of TCAM after bit flipping, we propose a novel TCAM cell design.
Simulation results show that compared to the original architecture, the bit-flipping technique can improves 16.84% of read SNM for data cells, 29.94% for mask cells, and reduces 12.95% of search time degradation. The power gating technique can improves 12.31% and 20.92% of the read SNM for data cells and mask cells, and reduce 17.57% of the search time degradation. In addition, 17.74% and 30.53% of the read SNM of data cells and mask cells can be improved, and 21.01% of search time degradation can be reduced when both techniques are used at the same time.

[1] BGP Routing Table Analysis Reports: http://bgp.potaroo.net/
[2] Y. Cao, et al. Predictive Technology Model (PTM). Available: http://www.eas.asu.edu/~ptm
[3] A. Chakraborty and D. Z. Pan, “Controlling NBTI degradation during static burn-in testing,” in Asia and South Pacific Design Automation Conference, pp. 597-602, 2011
[4] N. Hohn, K. Papagiannaki, and D. Veitech, “Capturing router congestion and delay,” IEEE/ACM Trans. on Networking, pp. 789-802, 2009
[5] K. Kang, M. A. Alam, and K. Roy, “Characterization of NBTI induced Temporal Performance Degradation in Nano-Scale SRAM array using IDDQ,” IEEE International Test Conference, pp. 1-10, 2007.
[6] T. T. Kim and Z. H. Long, “Impacts of NBTI/PBTI on SRAM Vmin and Design Techniques for SRAM Vmin Improvement,” International SoC Design Conference, pp. 163-166, 2011
[7] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Impact of NBTI on SRAM Read Stability and Design for Reliability,” International Symposium on Quality Electronics Design, pp. 6-11, 2006
[8] Y. Kunitake, T. Sato and H. Yasuura, “Signal Probability Control for Relieving NBTI in SRAM Cells,” International Symposium on Quality Electronic Design, pp. 660-666, 2010
[9] Y. Kunitake, T. Sato and H. Yasuura, “A Case Study of Short Term Cell-Flipping Technique for Mitigating NBTI degradation on Cache,” Asia Symposium on Quality Electronic Design, pp.301-307, 2010
[10] H. Mostafa, M. Anis and M. Elmasry, “Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells,” IEEE Trans. Circuits Syst. I, pp. 2859-2871, 2011
[11] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuit,” IEEE Trans. Comput.-Aided Design Integr. Circuit Syst., pp. 743-751, 2007
[12] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the Temporal Performance Degradation of Digital Circuits,” IEEE Trans. Electron Device Lett., pp. 560-562, 2005
[13] D. Shah and P. Gupta, “Fast Updating Algorithms for TCAMs,” IEEE Micro, vol. 21, no. 1, pp. 36–47, 2001
[14] E. Seevinck, F.J. List and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid State Circuits, 1987
[15] J. Shin, V. Zyuban, P. Bose and T. M. Pinkston, “A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime,” International Symposium on Computer Architecture, pp. 353-362, 2008
[16] T. Siddiqua and S. Gurumurthi, “Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays,” IEEE Annual Symposium on VLSI, pp. 393-398, 2010
[17] Renesas' TCAM product : http://www.renesas.com/products/memory/TCAM/index.jsp
[18] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design,” IEEE Design Automation Conference, pp. 1047-1052, 2006
[19] S. Wang, T. Jin, Chuanlei Zheng, and Guangshan Duan, “Low Power Aging-Aware Register File Design by Duty Cycle Balancing,“ Design, Automation & Test in Europe Conference & Exhibition, pp. 546-549, 2012
[20] W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, and Y. Cao, “Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology,” IEEE Trans. on Device and Materials Reliability, vol. 7, pp. 509-517, 2007
[21] Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, and H. Yang, “Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques,” IEEE Transactions on Very Large Scale Integration Systems, pp. 1-14, 2010
[22] Hao-I Yang, Shyh-Chyi Yang, Wei Hwang and Ching-Te Chuang, “Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM,” IEEE Trans. on Circuits and Systems, pp. 1239-1251, 2011
[23] Hao-I Yang, Wei Hwang, and Ching-Te Chuang, “Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-k-Metal-Gate Devices,” IEEE Trans.on VLSI systems, pp. 1192-1204, 2011
[24] S. Zafar, Y. H. Kim, V. Narayanan, C. Cabral Jr., V. Paruchuri, B. Doris, J. Stathis, A. Callegari and M. Chudzik, “A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates,” IEEE Symp. VLSI Technol. Dig. Tech. Paper, pp. 23-5, 2006
[25] S. Zafar, A. Kumar, E. Gusev, and E.Cartier, “Threshold Voltage Instabilities in High-k gate Dielectric Stacks,” IEEE Trans. on Device and Materials Reliability., pp. 45-4, 2005