隨著人工智慧與量子運算技術的迅速發展，對於低溫環境下穩定運作的電子元件的需求日益提升。為了同時實現高效能以及低功耗的目標，低溫操作之互補式場效電晶體（Cryogenic Complementary Field-Effect Transistor, cryo-CFET）被視為極具潛力之關鍵技術。鍺（Ge）憑藉其高載子遷移率與優異電性，適用於p型通道材料；而矽（Si）則因具備成熟製程基礎，持續於n型通道中扮演重要角色。
本論文實現異質通道之垂直堆疊Ge/Si CFET，採用Inversion Mode / Junctionless（IM/JL）結構，並透過低溫晶圓鍵合技術成功整合Ge與Si兩種材料於單一基板上。針對通道釋放製程中，由於濕蝕刻時間過長所導致之上層通道塌陷與下層通道未完全釋放問題，本文提出藉由增加鍵結氧化層厚度以提升通道穩定性之解決方案，有效改善元件結構完整性。本論文進一步地針對Ge pFET與Si nFET，分別改善閘極介電層介面品質、調整離子佈植的摻雜條件，並改良後續的活化製程，以降低接觸電阻並強化通道的導電能力。
本論文於300K、200 K、100 K、77 K及50 K等多種低溫條件下進行電性量測與分析。量測結果顯示，IM/JL Ge/Si CFET元件在低溫下於Ge PFET仍具備穩定的電流導通與關閉能力，且電流開關比( Ion/Ioff )隨著溫度的下降而有顯著的提升，此外，次臨界擺幅（Subthreshold Swing, SS）亦隨溫度下降而趨於陡峭，顯示閘極對通道的控制能力增強。然而，由於Junctionless結構對於摻雜均勻性與缺陷較為敏感，在Si NFET元件的表現受低溫影響的程度較大，尤其是在隨著溫度下降後出現的電流飽和現象。Ge PFET與Si NFET的臨界電壓（Vth）皆隨著溫度下降而出現偏移。
本論文結果顯示，Ge pFET具備良好的低溫操作潛力，適合作為低溫環境下穩定運作的電子元件選項，然而Si nFET於低溫下的導電行為仍需進一步製程優化，以提升整體CFET元件於低溫環境下的穩定性與可靠度。

With the rapid advancement of artificial intelligence and quantum computing technologies, the demand for electronic devices capable of stable operation under cryogenic environments has significantly increased. To simultaneously achieve high performance and low power consumption, cryogenic Complementary Field-Effect Transistors (cryo-CFETs) are considered a highly promising solution. Owing to its high carrier mobility and excellent electrical properties, germanium (Ge) is suitable as a p-type channel material, while silicon (Si) continues to play a vital role in n-type channels due to its well-established process maturity.
In this work, a vertically stacked Ge/Si CFET with heterogeneous channels is demonstrated, adopting an Inversion Mode/ Junctionless (IM/JL) architecture. Through low-temperature wafer bonding techniques, Ge and Si channels are successfully integrated onto a single substrate. During the channel release process, continued wet etching can result in upper channel collapse and incomplete release of the lower channel. To address this, we propose increasing the bonding oxide thickness to improve channel stability, effectively enhancing device structural integrity. Additionally, the Ge pFET and Si nFET are optimized by improving the gate dielectric interface quality, adjusting the ion implantation conditions, and improving the subsequent activation processes to reduce contact resistance and enhance channel conductivity.
Electrical characterizations were performed at various temperatures, including 300 K, 200 K, 100 K, 77 K, and 50 K. The results show that the IM/JL Ge/Si CFET exhibits stable on/off current switching in Ge pFETs under cryogenic conditions, with a notable improvement in the Ion/Ioff ratio as temperature decreases. Moreover, the subthreshold swing (S.S.) becomes steeper at lower temperatures, indicating enhanced gate control over the channel. However, due to the sensitivity of the junctionless structure to doping uniformity and defects, the Si nFET shows more obvious degradation at low temperatures, including current saturation behavior. Both Ge pFET and Si nFET exhibit threshold voltage (Vth) shifts as temperature decreases.
The results indicate that Ge pFETs have promising potential for low-temperature operation and are well-suited for cryogenic computing applications. Nonetheless, further process optimization is required to improve the conduction characteristics of Si nFETs under cryogenic conditions, thereby enhancing the overall stability and reliability of CFET devices in low-temperature environments.

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