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研究生：	許禮璿 Hsu, Li-hsuan
論文名稱：	積體電路銅導線製程之殘餘應力研究 Study on residual stress of VLSI interconnect structures
指導教授：	蔡錦俊 Tsai, Chin-Chun 羅光耀 Lo, Kuang-Yao
學位類別：	碩士 Master
系所名稱：	理學院 - 光電科學與工程研究所 Institute of Electro-Optical Science and Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	79
中文關鍵詞：	電鍍、銅、應力
外文關鍵詞：	stress, copper, electroplating
相關次數：	點閱：68 下載：7
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在積體電路的後段製程電鍍銅(Electrochemical Plating)的電流強度會影響到電鍍時銅晶粒(grain)的大小。而電鍍銅品質的好壞，對於銅導線的殘存應力(residual stress)和空缺(void)的產生有著極大的影響。因此在這個實驗中，利用不同的電鍍方式以穩定銅膜的殘存應力，進而抑止空缺的產生。以不同大小的晶粒堆疊來達到較高的堆積密度(packing density)和晶粒邊界(grain boundary)，使得銅膜本身能夠在短時間內僅靠著自我熱退火(self-annealing)而完成再結晶(recrystallization)。這不僅能夠提供品質
更佳的銅膜，還可以少了一道熱退火(thermal annealing)的製程，降低製程所耗費的成本。

Electroplated Cu films with different plating conditions are characterized to study the residual stress during annealing. An improved copper (Cu) process with strategy plating current was used to stabilize the residual stress and suppress the void formation. Grain growth during the process induces residual stress in the film. The Cu grain size is inverse proportional to the amplitude of the plating current in the electroplated process, and the plating
current dominates the density of the grain boundary due to the aggregation of Cu grain. Therefore the elimination of the grain boundaries happens in the first thermal cycle and generates a tensile residual
stress. The electroplated process by the improved strategy plating current was presented to produce various grain sizes to enhance the interface packing density of the Cu film. This result leads to a higher ensity of the grain boundaries and is helpful to the grain growth only by the effect of Cu self-annealing.
The residual stress keeps a stable value without the thermal treatment. This strategy plating method presents a reliable Cu interconnect process without considering the change in the residual stress.

摘要................................................. i
Abstract............................................ ii
Acknowledgement.................................... iii
Contents............................................ iv
List of Figures.................................... vii

Introduction......................................... 1

Chapter 1 Background................................. 2
1.1 Implantation and annealing....................... 2
1.2 Cu interconnect and dual damascene structure..... 3
1.3 Self-annealing of electro plated Cu.............. 5
1.4 Grain structure evolution during annealing 
    process.......................................... 6
1.5 Stress void and electromigration phenomena....... 6

Chapter 2 Theory.................................... 10
2.1 The Stoney formula.............................. 10
2.2 Curvature-based residual stress measurement: 
    Parallel beams Reflection....................... 12
2.3 Film stress from X-ray diffraction (XRD)........ 19
2.4 Development of stress in Cu films............... 25

Chapter 3 The correlation between residual stress 
          and Copper metallization.................. 28
3.1 Introduction: residual stresses in Cu 
    interconnects................................... 28
3.2 Sample preparation.............................. 29
    3.2.1 Fixed current plating..................... 29
    3.2.2 Three step pulse current plating.......... 30
    3.2.3 Programming step current plating.......... 32
3.3 Result and discussion........................... 33
    3.3.1 Fixed current plating..................... 33
    3.3.2 Three step pulse current plating.......... 35
    3.3.3 Programming step current plating.......... 37
3.4 Compare parallel beams reflection (PBR) and
    X-ray diffraction (XRD)......................... 39
    3.4.1 Fixed current density plating............. 39
    3.4.2 Three step pulse current plating.......... 41
    3.4.3 Programming step current plating.......... 44
3.5 Summary......................................... 50

Chapter 4 A strategy copper plating method without 
          annealing process......................... 51
4.1 Introduction: Electroplating and void formation. 51
4.2 Experimental.................................... 52
4.3 Result and discussion........................... 54
    4.3.1 The hysteresis stress loop and residual 
          stress.................................... 54
    4.3.2 Improved plating strategy................. 59
4.4 Summary......................................... 63

Chapter 5 The residual stress of Phosphorous and 
          Arsenic implanted Si through rapid thermal
          annealing................................. 64
5.1 Introduction: Si implantation................... 64
5.2 Experimental.................................... 66
5.3 Result and discussion........................... 68
5.4 Summary......................................... 74

Chapter 6 Conclusion................................ 75

References.......................................... 76
                                    

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校內：2010-06-24公開
校外：2010-06-24公開

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