隨著科技的持續進步，3C產品的功能繁多且運行速度快和體積輕巧已成為市場趨勢。3D封裝因此孕育而生。其中，矽穿孔(Through Silicon Via, TSV)是3D封裝關鍵技術之一，可使晶片層與層直接垂直互連，大幅度縮短傳輸距離且減小延遲和功耗，實現了高度異質晶片整合的目的。
本論文研究的主要重點分三個部分，分別探討不同的TSV幾何尺寸對信號完整性的影響、不同的TSV幾何結構對溫度的影響、以及TSV幾何結構對考慮溫度相依的信號完整性的影響，和觀察低頻與高頻運算下的載子遷移率分布情形。其中TSV幾何結構控制因子有導孔半徑、深度、間距、絕緣層厚度和Bump半徑及高度。
本研究結論歸納出TSV幾何尺寸對信號完整性影響之原因，統整出不同TSV幾何尺寸的溫度與運算頻率的關係、頻率與考慮溫度相依的信號損失變化關係，以及低頻運算與高頻運算下，TSV結構受熱應力擠壓，因壓阻效應所導致的載子遷移率分布結果。

Through Silicon Vias (TSVs) is important in three-dimensional packaging because they can be used to connect chips vertically to reduce the signal transmission distance and power consumption. Thus, TSVs can achieve the purpose of highly heterogeneous 3D wafer integration.
At high frequency operations, the temperature will become a non-negligible factor. A high temperature of the chip not only increases the signal transmission loss through TSV but also deforms the TSV structure due to thermal stress which in turn affects the carrier mobility. Therefore, in this thesis, finite element analysis is used to investigate the geometric effects of TSVs on signal integrity, operation temperature, and carrier mobility. The simulation results show that the operation temperature increases as the operation frequency increases, irrespective of the TSV radius. Also, for the lattice directions of <100> and <110>, the carrier mobility ratio of p-MOSFET is small in the direction of <100>; whereas it is <110> the n-MOSFET carrier mobility ratio to be small.

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