氮化鋁鎵/氮化鎵半導體之異質接面處將藉由優選c-自發極化(試片表面指向基板)之極化特性，使電子聚集於導帶的不連續面並受量子井位侷限其飄移方向而形成高濃度之二維電子氣(2DEG)通道，此通道擁有高電子遷移率以及高電子飄移速度等特性，更因氮化鎵本身為寬能隙半導體材料，使氮化鋁鎵/氮化鎵之異質結構半導體元件特性表現更能達到高崩潰電場、高溫以及高頻的工作等優勢。在本論文中，我們欲將以此氮化鋁鎵/氮化鎵異質結構製作空乏型(Depletion mode)及增強型(Enhancement mode)之金氧半高電子遷移率場效電晶體(MOS-HEMTs)，結合兩種不同形式元件並以共源極反相器(Common source inverter)電路架構下實現空乏型(常開；Normally on)元件與增強型(常關； Normally off)串聯之互補式金氧半高電子遷移率場效電晶體元件(CMOS-HEMTs)。
在增強型元件的部分，為了降低結構中氮化鋁鎵的極化效應，使得載子通道內電子濃度下降，於提升臨限電壓(Threshold voltage，V_TH)的同時更提升閘極控制能力，將採用光電化學(Photoelectronchemical，PEC)濕式蝕刻法完成閘極掘入結構製作，並透過脈衝雷射沉積法(Pulsed laser deposition technique)製作鈮酸鋰(Lithium niobate，LiNbO3)鐵電薄膜作為閘極氧化層，結合閘極掘入結構與該鐵電薄膜之自發極化特性相輔抵銷氮化鋁鎵/氮化鎵異質結構內之極化效應，達到空乏二維電子氣通道之效用，成功製做出增強型高速電子遷移率電晶體。
而於空乏型元件中，為使其形成一小電流形式之常開元件，並在共源極反相器電路中形成一負載式電晶體(Load type transistor)的操作模式，我們利用光電化學法進行濕式蝕刻製作閘極掘入結構，降低二維電子氣通道內載子濃度，使臨限電壓值有效地正移至靠近零的位置，同時使該元件仍保持在小電流的電晶體操作特性。
在不同的空乏型蝕刻深度下，元件將有不同增強型對空乏型之操作電流比值，有別於傳統利用閘極寬長比調變電晶體間電流比例的做法，此一互補式場效電晶體元件將擁有空乏、增強型兩電晶體尺寸面積相等的優勢，藉此而避免元件面積需隨電流比例放大的因素達到總面積相對縮小的特點，並且亦不影響該反相器作動的能力。
在氮化鋁鎵薄膜經蝕刻後所剩深度分別為12 nm、10 nm及8 nm的負載式空乏型元件下，我們可得其與增強型元件的電流比例分別為6、10以及25倍，並且經由負載線特性、時域輸出波型及輸出輸入轉移曲線等反相器各項特性趨勢中，我們可觀察得知互補式場效電晶體元件在25倍的操作電流比例下將擁有較好的反相器輸出特性，操作於V_DD= 5 V、V_IN = 5 V的條件下，輸出擺幅(Output Swing)：4.9 V、雜訊邊際(Noise Margin)：〖NM〗_H= 1.9 V、〖NM〗_L= 1.7 V，而當V_OUT=2.5 V (V_DD/2)時其V_IN值已約落於2.5 V(V_DD/2)位置，達到無偏斜反相器的輸出特性。
而最後我們藉由此蝕刻調變電流比例的做法，成功達到增強與空乏型元件皆以最小線寬的面積尺寸進行製作，完成互補式場效電晶體元件面積尺寸有效地降低、形成尺寸微縮之優勢。

In this research, the complementary metal-oxide-semiconductor high-electron-mobility transistors (CMOS-HEMTs) were integrated with the AlGaN/GaN Enhancement-mode (E-mode) and Depletion-mode (D-mode) transistors. The AlGaN/GaN HEMTs with the polarization-induced two dimensional electron gas (2DEG) channel were generally fabricated as the D-mode transistors. To fabricate the critical E-mode transistors, the ferroelectric LiNbO3 (LNO) film was deposited as the gate insulator on the photoelectrochemically (PEC) etched gate-recessed structure using a pulsed laser deposition (PLD) system. The simultaneous use of the ferroelectric LNO film and the gate-recessed structure could more effectively compensate the 2DEG channel at the AlGaN/GaN interface for fabricating the E-mode transistors. Besides, to form the unskewd inverter, the current ratio of E/D-mode transistors was adjusted with various etching depths in the AlGaN layer of the load type D-mode transistors. Compared to the typical tuning method, this etching process method was beneficial for scaling down the CMOS-HEMTs owing to the size match between the E/D-mode transistors. Finally, as the input signal was 5 V, the output swing of the resulting CMOS-HEMTs with the E/D-mode transistor current ratio (β) of 25 was 4.9 V, the noise margin high and low were about 1.9 V and 1.7 V respectively. From the voltage transfer curve (VTC), the corresponded V¬IN was about 2.5 V which equaled to VDD/2 as the V¬OUT was 2.5 V, which revealed that the resulting CMOS-HEMTs with the β of 25 could be operated as an unskewed inverter.

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