隨著製程技術的進步，單一晶片可容納的邏輯閘數目已遠遠超乎過去的想像。而數位時代的來臨，越來越多高複雜度的IC設計需求油然而生，此時傳統的IC設計方法已趕不上市場需求的速度，欲突破此一困境，需要由設計方法進行改造，提高電路設計的正確性，增加設計及驗證速度，以縮短產品上市時間。
　　本文提出一個新的漸進式硬體設計驗證流程，此流程從最一開始的C model到最後電路在FPGA上進行大量資料驗證皆涵蓋其中。整個流程以電路驗證做為設計上之基本考量，將電路所需要的測試資料，以及結果、乃至結果之比對，皆整合進本流程當中，而整個流程之產出，皆會在下一個階段被利用，而不會造成資源浪費。最後，我們以H.264視訊編碼系統為例，講解如何將本流程套用至實際應用當中。在我們的經驗中，這樣的設計流程能夠大大的減低耗費在驗證以及除錯等佔據了大部分產品開發的時間。

　　As the process technology growing, the total gate count in a single chip has farther beyond our imagination. Comes the digital age, there are more and more complex IC design requirements. In this situation, traditional IC design flow can not follow the highly growing and demanding requirements. For design breakthrough, we must make improvements from our design methodology, to increase the reliability, and speed up design and verification time, to cut down time to market.
　　In this thesis, a novel progressive hardware design/verification flow is proposed. This flow covers from the beginning of algorithm/system modeling/partitioning with C language model to the end of design verification on FPGA. Design verification is the main issue of this flow. The result produced in each design phase of the proposed design flow can be used in the verification of the next design phase. In addition, generating test vectors and comparing the results on both simulation model and real circuit in FPGA are also achieved during this flow. At the end of this thesis, we take currently popular video encoding system – H.264 as a design example, to explain this novel design flow. In our experiences the proposed design flow greatly reduces the time spent on verification and debugging which occupy most of the design time of a product.

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