簡易檢索 / 詳目顯示

研究生: 彭智群
Peng, Jhih-cyun
論文名稱: CMOS雜訊與頻率相依性之分析暨雙頻及寬頻低雜訊放大器之設計
Analysis of the CMOS Noise with Frequency Dependence and Designing Dual-band and UWB Low Noise Amplifiers
指導教授: 洪茂峰
Houng, Mau-Phon
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 70
中文關鍵詞: 頻率互補式金屬-氧化層-半導體雙頻低雜訊放大器超寬頻低雜訊放大器
外文關鍵詞: Dual-band low-noise amplifier (Dual-band LNA), Complementary Metal-Oxide-Semiconductor(CMOS), frequency, Ultra-wideband low-noise amplifier ( UWB LNA)
相關次數: 點閱:85下載:4
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 近年來無線通訊網路之快速發展,射頻積體電路以矽為基礎的整合性元件工作頻率在GHz時,因此在MOSFET需要準確的模型來得到精確之電路模擬結果,是很重要的,此外低雜訊放大器為射頻積體電路接收器的第一級,它不但提供放大接收的訊號而且降低訊號雜訊在整個系統。
    在本次論文中,我們主要研究分二部份,首先在第二章分析CMOS雜訊與頻率之相依性,同時閃耀雜訊為低頻主因雜訊,在高頻時為熱雜訊和閘極引發雜訊為主因雜訊,在更進一步探討,我們發現頻率在10GHz以上時,閘極引發雜訊更加的明顯。
    第二部份設計雙頻和超寬頻低雜訊放大器其操作頻率分別為2.4/5.2GHz和3.1GHz~10.6GHz.雙頻設計使用電感,電容元件當作輸入阻抗匹配,輸出部份架構結合串聯和並聯共振達到輸出匹配;超寬頻低雜訊放大器結合共閘級輸入阻抗匹配和共電流架構來實現低成本,低功率消耗。
    本論文中之電路設計是以TSMC 0.18 CMOS 製程之model進行模擬,並經CIC審核下線,最後完成晶片的量測。

    In the recently years, the wireless communication system network trends of high data transmission and internet everywhere are increased day by day. As the operation frequency of Si-base integrates circuit’s increases to the gigahertz range for RF applications. Therefore, the MOSFET has requirement accurate noise model in the high frequency to predicative simulation result which is more important. On the other hand, The Low Noise Amplifier is the first block of the RF receiver. It not only provides enhanced received signals but also reduces the noise of the whole system.
    This thesis primarily contains two parts. First, the analysis of analysis of the CMOS noise with frequency dependence in the chapter 2 as we know the 1/f noise dominates at low frequency. Meanwhile, thermal noise and the induced-gate noise dominate at high frequency. For more discussion details in chapter 2 that we find it significant that the induced-gate noise floor becomes obvious when the frequency is above 10GHz.
    Second, the design Dual-band and UWB LNA respectively operate 2.4/5.2GHz and 3.1GHz ~10.6GHz are respectively. The Dual-band LNA using L-C component to create dual-band input impedance matching resonance and the output part architecture combine series resonance and Parallel resonance together to achieve output matching and later devised UWB LNA combine common gate for input matching and Current-Reuse with circuit architecture to accomplish low cost and low power consumption.
    The experiment of designing Dual-band and UWB LNA with TSMC 0.18 m CMOS technology applies for CIC tapeout verification. Finally, we had measured IC chip.

    Contents........................................................................................................viii List of Figures ........................................................................ x List of Tables..........................................................................xiii Chapter 1 Introduction ................................................................ 1 1.1 Motivation ................................................................................... 1 1.2 Thesis Organization......................................................................... 2 Chapter 2 Basic Concepts in the CMOS noise with Frequency dependence................. 4 2.1 Induction .................................................................................... 4 2.2 Two-Port Network ............................................................................ 4 2.2.1 Noisy Two-Port Network............................................................... 5 2.3 Advanced Noise analysis ........................................................................... 7 2.3.1 Extrinsic Noise ........................................................................................... 7 2.3.1.1 Flicker noise .................................................................................... 8 2.3.2 Intrinsic Noise ............................................................................... 11 2.3.2.1 Include channel thermal noise....................................................... 11 2.3.2.2 Induced-gate noise. ........................................................................... 12 2.4 Analysis of Noise in Different Frequency .................................................... 15 2.5 Conclusion....................................................................................... 20 Chapter 3 Basic Concepts in Dual-band LNA Design .................................... 21 3.1 Introduction ....................................................................................... 21 3.2 Dual-band Receivers system............................................................... 21 3.3 Design the Theory of Dual-band LNA................................................... 23 3.3.1 LNA topologies...................................................................... 23 3.3.2 Gain compression and Intermodulation...................................... 26 3.3.3 Stability............................................................................. 28 3.3.4 Dual-band LNA circuit topology............................................... 28 3.3.4 Dual-band LNA circuit topology............................................... 29 3.4 Simulation and Measurement Result............................................. 32 3.4.1 Chip Implementation ........................................................... 43 3.5 Conclusion................................................................................................................ 44 Chapter 4 UWB CMOS LNA Design .............................................................................. 46 4.1 Introduction ............................................................................. 46 4.2 UWB Receivers system............................................................. 46 4.3 Design the Theory of UWB LNA................................................. 48 4.3.1Gain flatness technique ....................................................... 48 4.3.2 UWB LNA circuit topology ................................................... 49 4.4 Simulation and Measurement Result................................................. 53 4.5 Conclusion................................................................................. 62 Chapter 5 Conclusions and Future work ........................................... 65 Future work.................................................................................... 66 References ............................................................................................ 67

    [1] Derek K. Shaeffer, Thomas H. Lee,”A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE JOURNALOFSOLID-STATE CIRCUITS, VOL. 32, NO. 5, MAY 1997.
    [2] Thomas H. Lee,”The Design of CMOS Radio-Frequency integrated Circuits: Chapter 12 Lna design” Cambridge university express, Second Edition 2004.
    [3] J.H. Huang, Z.H. Liu, M.C. Jeng, P.K. Ko, C. Hu, “A Robust Physical and Predictive Model for Deep-Sub micrometer MOS Circuit Simulation”, IEEE Custom Integrated Circuits Conference, Pages:14.2.1~4, 1993.
    [4] T. Warabino, M. Miyake, N. Sadachika, D. Navarro, Y. Takeda, G. Suzuki, T. Ezaki,M. Miura-Mattausch,H. J. Matanuska, T. Ohguro*, T. Iizuka*, M. Taguchi*,S. Kumashiro* and S. Miyamoto, ”Analysis and Compact Modeling of MOSFET
    High-Frequency Noise”, Simulation of Semiconductor Processes and Devices, 2006 International Conference on, Pages:158 – 161, Sept. 2006.
    [5] Chih-Hung Chen1*2, M. Jamal Deed and Mishel Matloubian2 and Yuhua Chcng, “Extraction of the Channel Thermal Noise MOSFETs, Microelectronic Test Structures”, 2000. ICMTs 2000 Proceeding s of the 2000 international conference on, Pages:42 – 47, 2000.
    [6] Christian C.EnZ Eric A. Vittoz,” Charge-based MOS Transistor Modeling: Chapter Introduction”, WILEY express, 2006.
    [7] L. Chua, C. Desoer and E. Kuh,”Linear and Nonlinear Circuits, New York”: McGraw- Hill, 1987.
    [8] David M. Pozar,” MICORWVE ENINERRING: Chapter 4 Microwave network analysis”,University of Massachusetts at Amherst, WILEY express, Third Edition 2005.
    [9] GEORGED.VENDELIN, ANTHONY M.PAVIO, ULRICH L. ROHDE,” Microwave Circuit Design Using Linear and Nonlinear Techniques: Chapter 7 Noise in linear two-ports”,WILEY express, 2006
    [10] P. R. Gray and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits: Chapter 3 Single-Transistor and Multiple-Transistor Amplifiers”, Wiley express, Fourth edition 2004.
    [11] C. H. Huang, H. Y. Li, Albert Chin, V. Liang', and S. C. Chien‘ Dept. of FlextronicsEng., National Chiao Tung Univ., Hsinchu, TaiwanUnited Microelectronics Coperation, Hsinchu, Taiwan ,“Optimized Noise and Consistent RF Model for 0.18μm MOSFETs”, VLSI Technology, Systems, and Applications, 2003 International Symposium on,Pages:109 - 112 6-8 Oct. 2003.
    [12] S.Christensson, I. Lundstrom, and C. Svensson, “Low Frequency Noise in MOS Transistors—I Theory”, Solid-state Elec., Vol., pp. 797,812, 1968.
    [13] A.L. McWhorter, Semiconductor Surface Physics, R. H. Kingston, Ed. Philadelphia, PA: Univ. Pennsylvania Press, 1957.
    [14] Yael Nemirovsky, Fellow, IEEE, Igor Brouk, and Claudio G. Jakobson , “1/f Noise in CMOS Transistors for Analog Applications”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001.
    [15] Christian Enz, Member, IEEE, “An MOS Transistor Model for RF IC Design Valid in All Regions of Operation”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002.
    [16] Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng,Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui,Jianhui Huang, Robert Tu, Ping K. Ko
    and Chenming Hu,” BSIM3v3.2.2 MOSFET Model Users’ Manual”, Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720,1999.
    [17] Yuhua Cheng, M. Jamal Dee ,Chih-Hung Chen,”MOSFET Modeling for RF IC Design, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005.
    [18] Xiaodong Jin, Jia-Jiunn Ou, Chih-Hung Chen*, Weidong Liu, M. Jamal Deen*, Paul R. Gray, and Chenming Hu,”An Effective Gate Resistance Model for CMOS RF and Noise Modeling”,Electron Devices Meeting, 1998. IEDM '98 Technical Digest, International. Pages:961 - 964 6-9 Dec 1998.
    [19] Reza Navid,” Amplitude and Phase Noise in Modern CMOS Circuits” Dept. of Electrical Engineering Stanford University, 2004.
    [20] F. Danneville, H. Happy, G. Damrine, J.Maxence, and A. Cay,” Microscopic Noise Modeling and Macroscopic Noise Models: How Good a Connection? ”,IEEE Trans. Electron Devices, 41, 779, 1994.
    [21] Pietro Andreani, Henrik Sjland,”Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier”,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING VOL. 48, NO. 9, SEPTEMBER 2001.
    [22] Chih-Hung Chen1*2, M. Jamal Deed and Mishel Matloubian2 and Yuhua Chcng, “Extraction of the Channel Thermal Naise MOSFETs”, Microelectronic Test Structures, 2000. ICMTs 2000. Proceeding s of the 2000 international conference on, Pages:42 – 47, 2000.
    [23] R. Srinivasana and Navakanta Bhatb,“Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors”, JOURNAL OF APPLIED PHYSICS 99, 084505, 2006.
    [24] T. Warabino, M. Miyake, N. Sadachika, D. Navarro, Y. Takeda, G. Suzuki, T. Ezaki, M. Miura-Mattausch,H. J. Mattausch, T. Ohguro*, T. Iizuka*, M. Taguchi*, S. Kumashiro* and S. Miyamoto*,”Analysis and Compact Modeling of MOSFET High-Frequency Noise”, Simulation of Semiconductor Processes and Devices, 2006 International Conference on, Pages:158 – 161,Sept. 2006.
    [25] C. H. Huang, H. Y. Li, Albert Chin, V. Liang', and S. C. Chie “Optimized Noise and Consistent RF Model for 0.18μm MOSFETs”, VLSI Technology, Systems, and Applications International Symposium on. 6-8 Oct, Pages:109 - 112, 2003.
    [26] Chien-Chih Ho; Chin-Wei Kuo; Yi-Jen Chan; Lien, W.-Y.; Guo, J.-C.; “0.13- m RF CMOS and Varactors Performance Optimization by Multiple Gate Layouts”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 51, Issue 12, Pages:2181-2185 Dec. 2004.
    [27] Hossein Hashemi, Ali Hajimiri,“Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applications”, IEEE Transactions on Microwave Theory and Techniques, vol. 50, pp. 288-301, Jan 2002.
    [28] Meriam Ben Amor, Ahmed Fakhfakh,Hassene Mnif and Mourad Loulou, ,“Dual Band CMOS LNA Design With Current Reuse Topology”, Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on 2006, Pages:57 – 61, 2006
    [29] Thomas H. Lee,” The Design of CMOS Radio-Frequency integrated Circuits: Chapter 12 Lna design”, Cambridge university express, Second Edition 2004
    [30] Behzad Razavi, “RF Microelectronics: Chapter 2, Basic Concepts in RFDesign”, Prentice Hall Communication Engineering and Emerging Technology Series, 1997.
    [31] Guillermo Gonzalez,”Microwave Transistor Amplifiers Analysis and Design: Chapter 3 Microwave transistor amplifier design”,Prentice Hall express, Second edition 1997.
    [32] Y. P. Zhang, K. W. Chew, P. F. Wong,” Analysis and design of a fully integrated CMOS low-noise amplifier for concurrent dual-band receivers”, International Journal of RF and Microwave Computer-Aided Engineering,Vol 16, Issue 5, Pages: 444-453, September 2006.
    [33] Trung-Kien Nguyen, Sang-Gug Lee,” A Sub-mA, High-Gain CMOS Low-Noise Amplifier for 2.4 GHz Applications”, Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, Pages:4 pp, 21-24 May 2006.
    [34] Oppermann, Ian, Hamalainen, Matti, Iinatti Jari. “UWB theory and applications: Chapter 1 Induction” Wiley express, 2004
    [35] Ultra-wideband Technology for Short-Range, High-Rate Wireless Communications; Jeff Foerster, Intel Labs; http://www.ieee.or.com/Archive/uwb.pdf.
    [36] UWB Development, Institute of Microelectronics (IME), Singapore UWB Community. Available: http://uwb.tech.org.sg/devResIme.html.
    [37] Ke-Hou Chen, Jian-Hao Lu, Bo-Jiun Chen, and Shen-Iuan Liu,“An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-m CMOS”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 3 MARCH 2007.
    [38] Vishwakarma, S Sungyong Jung; Youngjoong Joo,”Ultra wideband CMOS low noise amplifier with active input matching”, Ultra Wideband Systems, 2004. Joint with Conference on Ultrawideband Systems and Technologies Joint UWBST & IWUWBS. 2004 International Workshop on, Pages:415 - 419, 18-21 May 2004.
    [39] Xiaohua Fan; Sanchez-Sinencio, E.; Silva-Martinez,”A 3GHz-10GHz common gate ultra wideband low noise amplifier”, Circuits and Systems, 2005. 48th Midwest Symposium on, Vol. 1, 7-10 Aug, Pages:631 - 634, 2005.
    [40] Yi-Jing Lin; Hsu, S.S.H.; Jun-De Jin; Chan, C.Y,”A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier with Current-Reused Technique”, Microwave and Wireless Components Letters, IEEE, Pages:232 - 234, Volume 17, Issue 3, March 2007.
    [41] Guillermo Gonzalez,”Microwave Transistor Amplifiers Analysis and Design: Chapter 3 Microwave transistor amplifier design”, Prentice Hall express, Second edition 1997.
    [42] A .Bevilacqua and A.M Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6GHz wireles receivers”, ISSCC T Tech. Dig .382-383, 2004.
    [43] Kao, H.L.; Chin, A.; Chang, K.C.; McAlister, S.P.,”A Low-Power Current-Reuse LNA for Ultra-Wideband Wireless Receivers from 3.1 to 10.6 GHz”, Silicon Monolithic Integrated Circuits in RF Systems, 2007 Topical Meeting on, Pages:257 – 260, 10-12 Jan. 2007.
    [44] Chang-Tsung Fu; Chien-Nan Kuo ,“3~11GHz CMOS UWB LNA using dual feedback for broadband matchin,”IEEE Radio Frequency Integrated Circuit (RFIC), pp. 53-56, June. 2006.
    [45] Chih-Fan Liao; Shen-Iuan Liu,” A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receiver”, Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005, Pages:161 - 164 ,18-21 Sept. 2005.

    下載圖示 校內:2011-01-16公開
    校外:2011-01-16公開
    QR CODE