本研究以探討低溫水熱法製備氧化鋅奈米結構應用於薄膜電晶體為主軸，主要分為兩研究方向，生長規律性排列之氧化鋅奈米結構及不同熱處理溫度對於薄膜電晶體電特性影響。
於生長規律排列氧化鋅奈米結構部分，本研究利用調配水熱法中溶液濃度及晶種層厚度條件，比較不同變因下奈米柱生長形態。最終利用溶液濃度 0.025 M 及晶種層 200 nm ，此條件具最佳氧化鋅奈米結構之生長均勻性及奈米柱準直性。本研究於源-汲極間加入擋層結構並搭配低溫水熱法製作氧化鋅奈米柱通道層，擋層結構部分可有效促使源極與汲極端所生長氧化鋅奈米結構具有單向性生長並可控制生長範圍，最終所製備薄膜電晶體具有規則排列之氧化鋅奈米結構。
低溫水熱法成長氧化鋅奈米柱，其結構本身具有高密度氧缺陷存在，故初步合成之氧化鋅奈米柱直接應用於薄膜電晶體通道，其奈米結構部分將具高導電性，使得元件喪失電晶體功能。
於本研究中，為了使氧化鋅奈米結構之缺陷密度有所降低，利用高濃度氮氣分別進行200oC、300oC 與400oC熱處理，並進行光致螢光量測，於300oC 熱處理之光致螢光量測中，與其餘條件相比下，具最高之紫外光與可見光發射比，應用於薄膜電晶體當中，因較低薄膜缺陷密度，於次臨界擺幅與轉移電導部分皆有所提升，其值分別為次臨界擺幅0.44 V / dec、轉移電導10.57 µS，另外開關電流比部分約為104，臨界電壓2.67 V，成功將規律生長之氧化鋅奈米結構應用於薄膜電晶體當中 。

In this study, the retaining layer and optimized parameters are used to overcome the problem of non-directionality nanostructure growth by hydrothermal method. The zinc oxide nanostructure with regular arrangement are prepared and applied to the channel layer of thin films transistors. Using change the heat treatment temperatures to improve the problem of high defect density exist in zinc oxide generate by low temperature hydrothermal method. Finally, the zinc oxide nanostructure arranges regularly to fabricate thin film transistors. After annealing process, enhance performances of device with subthreshold swing of 0.44 mV/dec, transconductance 10.57µS ,and on/off current ratio of 104.

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