本論文提出一個應用於軟體無線電(SDR)基於N徑濾波器具雜訊抑制之接收器前端電路，應用工作頻率範圍由433百萬赫茲至24億赫茲。
低雜訊放大器(LNA)以共閘極(CG)放大器實現，其中再利用放大器的電流源，形成一供雜訊抑制的回授迴路。一前授N徑濾波器與一主動混頻器由25%責任週期脈波產生器驅動，其中N徑濾波器將負載的低通響應轉移至射頻提供窄頻的阻抗匹配。此外，25%責任週期脈波由一組除頻器產生，輸出的 I/Q 訊號由兩組雙端轉單端輸出緩衝級推動至輸出。原型電路晶片由台積電90奈米 1P9M 金氧互補式半導體製程實現。由模擬結果得知，在考慮的操作頻段下，主電路提供 20.9分貝至22.4分貝的轉移增益。並且由量測結果得知，雜訊指數(NF)為6.8分貝至8.4分貝。主電路的輸入三階截止點(IIP3)為 -8.5 dBm。接收器前段電路在1.2伏特的電源供給下，僅消耗2.62毫瓦。25%責任週期脈波產生器的功率消耗，隨著操作頻率由433百萬赫茲至24億赫茲，消耗功率由8.1毫瓦至18.5毫瓦。

This thesis proposes a noise-cancellation receiver front-end based on an N-path filter for software-defined radio (SDR) applications from 433 to 2400 MHz.
The low noise amplifier (LNA) utilizes a differential common gate (CG) amplifier in which the tail current re-uses as a feedback loop for noise cancellation. A feedforward N-path filter and an active mixer driven by a 25% duty-cycle clock generator are stacked to transfer low-pass response to RF for narrow-band input matching. In addition, 25% duty-cycle clocks are generated by a frequency divider. Two differential-to-single output buffers delivery I/Q output. The prototype chip is implemented in TSMC 90 nm 1P9M CMOS process. The simulation results show that the conversion gain of the core circuit varies from 20.9 to 22.4 dB over the considered bands. Moreover, the measured noise figure (NF) ranges from 6.8 to 8.4 dB. The input third-order intercept point (IIP3) is -8.5 dBm. The core circuit of receiver front-end consumes 2.62 mW from a 1.2 V supply. The 25% duty-cycle generator consumes 8.1 to 18.5 mW within LO frequency from 433 to 2400 MHz.

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