隨著電晶體特徵尺寸的持續微縮，接面深度也便得越來越淺，伴隨而來的是元件製作在製造技術上變得更加難以控制。在 32 奈米製程或是更先進的製程技術上，因離子佈植後所產生的缺陷需要能更有效的抑制或是完全的消除，改善瞬間增益擴散效應(Transient Enhanced Diffusion)、短通道效應 (Short Channel Effect) 及臨限電壓 (Threshold Voltage) 之相關問題亦是先進製程所需克服的難題之一。製程技術的演進，超淺接面的應用對於傳統的快速回火機制 (RTP)，在溫度上的要求是越來越低，但這也導致硼 (B) 會發生表面鈍化、聚合 (inactivation and clustering) 及瞬間增益擴散效應 (TED) 效應在環型佈植 (Halo/Pocket Implantation) 及通道上更加嚴重化。為了改善短通道效應 (SCE)，高劑量摻雜的使用是必然的，但相對的影響則是使得元件在臨限電壓的限定電壓上會變得更加難以控制。缺陷的產生或殘留是從離子佈植後便存在，即使在 源極/汲極 (Source/Drain) 經過了快速熱回火製程 (RTP) 及雷射回火 (LRTP) 的高溫回火下還是依舊殘留著些許的缺陷，同時這些缺陷的產生也影響到元件漏電流的增加。
於 Wafer Acceptance Test (WAT) 電性量測中，我們從PN 接面參數中驗證出，在使用全低溫條件時的漏電流數據比起一般傳統室溫條件有著大約近 1.3x 的改善，同時Ion-Ioff 有著約 3% 的提升，且DIBL參數並沒有因此而衰退。在進一步的實驗當中，我們在摻雜步驟中實驗了幾組低溫組合的搭配分析，結果顯示，只需在nSDE Layer中使用Ge及C元素及nS/D Layer中使用As及P元素，就能達到與全低溫條件中相同的電性結果。

Due to the dimension scaling down of CMOS, the depth of ultra shallow junction (USJ) becomes more shallower, the following problems cause the difficulty of device performance control. The implantation induced defect engineering becomes more critical at 32nm and beyond. The improvement of transient enhanced diffusion (TED), short channel effect (SCE) and threshold voltage (Vth) variability is concerned and needed in advanced CMOS fabrication. The continuous USJ scaling requires lower spike annealing temperature via rapid thermal processing (RTP) which induces boron inactive and clustering, or causing more serious TED effect in channel or halo region. Besides, in order to improve SCE, a higher dosage is required but with degraded Vth variation for scaled USJ devices. Defects remained in pre-amorphization implantation (PAI) even though the RTP and laser spike annealing (LRTP) of source/drain (S/D) layer are applied, and they are responsible for the device leakage.

To maintain abrupt junction profiles, germanium (Ge) PAI and carbon (C) co-implants were applied before BF2 halo implantation. The incorporated carbon helps to suppress boron TED and enhances dopant activation, it also forms interstitial/clusters and reduces the formation of extended defects. Now in this thesis, The main idea is on the use of cryogenic ion implantation technology and its reduction of defects with several species (like Ge, C, etc.) used and to find out the critical step of using cryogenic feature simultaneously.

The whole cryo-implantation condition shows a better result than room temperature condition with leakage current improvement of 1.3x, Ion-Ioff improvement of 3%, and without DIBL degradation. Experiments based on split conditions for the cryo-implantation process with nSDE Layer @ Ge + C and nS/D Layer @ As + P show a comparable gains as compared with the whole cryo-implantation condition. Though the improvement in the leakage current is not obvious, the proposed cryo-implantation technology is expected to be a prospect tool for USJ engineering.

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