本論文將利用應變矽鍺材料優異的電洞傳輸特性及和矽材料之間形成的能帶工程，來研製P型摻雜異質接面場效電晶體。文中的P-型摻雜是以能將摻雜控制在數個原子層的高平面摻雜為主，並且我們將導入元件結構之設計。材料分析方面，我們將探討以超高真空化學氣相沉積法成長之高平面摻雜矽層，以及固體源分子束磊晶法成長之高平面摻雜矽鍺層，並以二次離子質譜儀及穿透式電子顯微鏡來分析其摻雜的分布及磊晶的品質。
在元件研製部份，包含以高平面摻雜作為載子提供層或者作為傳輸通道之矽鍺/矽異質接面金屬-半導體接面場效電晶體將被探討，包括反向調變式摻雜場效電晶體、通道摻雜場效電晶體及將通道摻雜場效電晶體成長在SOI (Silicon-on-insulator)基板上。由實驗結果可得知，所研製之元件具有高元件線性度，此也意味著所研製之電晶體將是具有前瞻性的技術之一。

In this dissertation, we utilize the improved hole transport characteristics and energy bandgap engineering in strained SiGe/Si heterojunction to implement p-type doped heterostructure filed-effect transistors (HFETs). Delta doping, which is a highly doping technique within a few monolayers, will be also adopted in the device design. Delta-doped Si grown by ultra high vacuum chemical vapor deposition (UHV/CVD) and delat doped SiGe grown by solid source molecular beam epitaxy (SSMBE) are analyzed by secondary-ion mass spectroscopy (SIMS) and cross-sectional transmission electron micrograph (TEM) instruments.
Then a series of devices with delta doped layer as carrier supplying layer or the conducting channel are fabricated, including inverted modulation-doped field-effect transistor (MODFET), delta-doped-channel field-effect transistor (DDCFET), and DDCFET grown on SOI (silicon-on-insulator). According to the experimental results, the excellent device linearity had been observed in DCFET, which means DCFET is a promising candidate for transistor performance enhancement.

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