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研究生: 張毓藍
Chang, Yu-Lan
論文名稱: 以錫膏印製銲錫隆點之電性與材料反應 行為研究
Investigations on the Electrical Properties and Material Reaction Behavior of Solder Bumps Produced by Stencil Printing
指導教授: 林光隆
Lin, Kwang-Lung
學位類別: 碩士
Master
系所名稱: 工學院 - 材料科學及工程學系
Department of Materials Science and Engineering
論文出版年: 2003
畢業學年度: 91
語文別: 中文
論文頁數: 98
中文關鍵詞: 銲錫隆點電性錫膏網印
外文關鍵詞: solder bump, solder paste printing, electrical property
相關次數: 點閱:175下載:5
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  • 本研究首先探討以錫膏網印方式製作的銲錫隆點(Solder Bump),經過不同可靠度測試環境條件的試驗後,所發生的界面反應和其剪力強度變化,並進一步了解其破壞機制;並將銲錫隆點以覆晶接合的方法,配合晶片和基板所設計的線路以量測電性變化,探討經不同環境條件試驗後銲錫接點的阻抗變化與材料反應行為的關係。

    觀察銲錫隆點界面反應可知,以Ni-P/Au作為銲錫隆點底層金屬會生成Ni3Sn4,經時效熱處理後,銲錫和Ni3Sn4間會生成(AuXNi1-X)Sn4化合物,時效溫度越高其生成量越多,進而會抑制Ni3Sn4化合物的成長。從剪力測試的實驗結果得知,初始重流(reflow)完成的銲錫隆點其剪力強度約為50g,且剪力測試後之破斷面皆位於鉛錫合金中,經過多次重流、高溫時效和恆溫恆濕試驗後,銲錫隆點剪力強度會隨重流次數和熱處理時間增加而降低,且下降幅度最大是經多次重流試驗,其次是高溫時效試驗,最小為恆溫恆濕試驗,所有試驗的破斷位置都位於鉛錫合金,表示其剪力強度下降並不受到介金屬化合物的影響,可見經可靠度試驗後銲錫界面間的結合強度仍優於鉛錫合金。

    覆晶接合試片經不同環境條件試驗後,從多次重流、高溫時效試驗發現,銲錫接點阻抗會隨著介金屬化合物成長而增加,此外銲錫接點在高溫時效環境下其阻抗值還會受高溫氧化和缺陷減少等因素影響。另外經恆溫恆濕和熱循環試驗後,可以發現在這兩種環境試驗下容易使得銲錫接點阻抗大幅上升,而導致其大幅上升的主因並不是介金屬化合物成長。經恆溫恆濕試驗之結果,推測其可能因素為濕氣造成部份線路腐蝕短路以及銲錫氧化,使得平均阻抗增加;熱循環試驗則由於材料間熱膨脹係數不同,產生熱應力導致裂縫生成,除了減少銲錫接點接觸面積,最終還可能造成整個銲錫接點斷路。

    The objective of this research was to investigate the mechanical and electrical properties of solder bumps produced with solder paste by printing. The shear strength of solder bumps and the interfacial reaction behavior between solder and UBM was investigated after reliability tests. Besides, it was also to measure the electrical resistance of flip chip bonded solder joints and to investigate the correlation between the change of the electrical resistance and the reaction behavior of the materials after different environmental tests.

    The interfacial investigation of solder bump indicated that Ni3Sn4 was formed. It was also observed that the (AuXNi1-X)Sn4 was formed between the Ni3Sn4 layer and solder after aging. A raise in aging temperature enhances the growth of (AuXNi1-X)Sn4 and inhibits the growth of Ni3Sn4. The average shear strength of solder bumps after reflow was about 50g, and the fracture occurred at the solder. It was also found that the shear strength of solder bumps was decreased with reflow times and aging time. But the fracture still occurred at the solder after reliability tests. The experimental results revealed that the lowering in shear strength was not induced by intermetallic compounds. The intermetallics exhibit a good adhesion between solder and UBM after reliability tests.

    The electrical test results showed that the increase of electrical resistance of solder joints after the multiple reflow test and high temperature storage test was ascribed to the growth of intermetallic compounds. In addition, the oxidation of solder and elimination of defects also affect the electrical resistance of the annealed solder joints. Furthermore, it was found that the electrical resistance of the solder joints greatly increases after the humidity-temperature test and thermal cycling test. The humidity-temperature test affect the electrical resistance of solder joints through the circuit corrosion and oxidation of solder. The thermal cycling test resulted in the formation of crack which caused the solder joint failure.

    總目錄 中文摘要……………………………………………………………Ⅰ 英文摘要……………………………………………………………Ⅱ 總目錄………………………………………………………………Ⅳ 表目錄………………………………………………………………Ⅵ 圖目錄………………………………………………………………Ⅶ 第壹章 簡介…………………………………………………………1 1-1覆晶接合技術……………………………………………………1 1-1-1覆晶接合的特點………………………………………………1 1-2覆晶接合製程……………………………………………………3 1-2-1網版印刷製程………………………………………………3 1-2-2銲錫隆點接合………………………………………………6 1-3銲錫隆點材料……………………………………………………6 1-4覆晶構裝中影響電性的相關機制………………………………13 1-4-1介金屬化合物…………………………………………………13 1-4-2環境應力………………………………………………………17 1-5研究目的…………………………………………………………20 第貳章 實驗方法與步驟……………………………………………21 2-1實驗構想與設計…………………………………………………21 2-2銲錫隆點製作……………………………………………………21 2-2-1矽晶片前處理…………………………………………………21 2-2-2微影與對位製程………………………………………………21 2-2-3濺鍍與剝膜製程………………………………………………26 2-2-4無電鍍析鍍製程………………………………………………29 2-2-5感光型聚亞醯胺之微影製程…………………………………29 2-2-6錫膏網印製程…………………………………………………34 2-3晶片接合…………………………………………………………34 2-4環境試驗…………………………………………………………34 2-5銲錫隆點性質分析………………………………………………38 2-5-1銲錫隆點剪力強度測試………………………………………38 2-5-2覆晶接點阻抗量測……………………………………………38 2-5-3銲錫隆點破壞結構與界面反應分析…………………………41 第參章 結果與討論…………………………………………………43 3-1銲錫隆點錫膏網印製程結果……………………………………43 3-2銲錫隆點可靠度分析……………………………………………43 3-2-1銲錫隆點在不同的環境條件下的界面反應…………………47 3-2-1-1多次重流試驗後銲錫隆點界面反應分析…………………47 3-2-1-2高溫時效後銲錫隆點界面反應分析……………………51 3-2-1-3恆溫恆濕試驗後銲錫隆點界面反應分析………………59 3-2-1-4不同環境試驗對介金屬化合物厚度的關係……………59 3-2-2不同環境試驗對銲錫隆點剪力強度的影響…………………59 3-2-2-1高溫時效和恆溫恆濕試驗對銲錫隆點剪力強度的影響………………………………………………………………………63 3-2-2-2多次重流試驗對銲錫隆點剪力強度的影響……………63 3-3銲錫隆點電性分析………………………………………………67 3-3-1多次重流試驗對銲錫接點阻抗的影響………………………67 3-3-2高溫時效試驗對銲錫接點阻抗的影響………………………71 3-3-3恆溫恆濕試驗對銲錫接點阻抗的影響………………………78 3-3-4熱循環試驗對銲錫接點阻抗的影響…………………………84 3-3-5不同環境下銲錫接點的電性比較……………………………89 第肆章 結論…………………………………………………………91 參考文獻………………………………………………………………92

    1.李宗銘, “異方性導電膠材料技術與應用”, 工業材料147期, 1999, pp. 93~98.

    2.J. H. Lau, Flip Chip Technologies, McGraw-Hill, New York, 1995, Chapter 1.

    3.楊省樞, “覆晶技術”, 工業材料127期, 1997, pp. 90~96.

    4.J. H. Lau, Flip Chip Technologies, McGraw-Hill, New York, 1995, Chapter 3.

    5.許坤賜, 電鍍參數對銲錫隆點均勻性影響及可靠度性質分析, 國立成功大學碩士論文, 民國八十八年, pp. 1~6.

    6.高田信司著, 林振華和林振富編譯, 高密度多層電路板技術, 全華科技圖書股份有限公司, 民國九十年, Chapter 2.

    7.張人傑, “覆晶接合方法評估”, 電子與材料第1期, 1999, pp. 43~46.

    8.陳偉亮, 異方向性導電膠覆晶接合之研究, 國立成功大學碩士論文, 民國八十九年, pp. 9~15.

    9.孔令臣, “覆晶凸塊技術”, 工業材料139期, 1998, pp. 155~161.

    10.L. Li and P. Thompson, “Stencil Printing Process Development for Flip Chip Interconnect”, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 23, No. 3, July 2000, pp. 165~170.

    11.J. Kloeser, K. Heinricht, E. Jung, L. Lauter, A. Ostmann, R. Aschenbrenner, and H. Reichl, “Low Cost Bumping by Stencil Printing: Process Qualification for 200 µm Pitch”, Microelectronics and Reliability, Vol. 40, March 2000, pp. 497~505.

    12.G. A. Rinne, ”Solder Bumping Methods for Flip Chip Packaging”, 1997 Electronic Components and Technology Conference, 47th, May 1997, pp. 240~247.

    13.C. L. Wong, and J. How, “Low Cost Flip Chip Bumping Technologies”, 1997 IEEE/CMPT Electronic Packaging Technology Conference, Singapore, IEEE, October 1997, pp. 244~245.

    14.R. H. Uang, K. C. Chen, S. W. Lu, H. T. Hu, and S. H. Huang, “The Reliability Performance of Low Cost Bumping on Aluminum and Copper Wafer”, 2000 Electronic Packaging Technology Conference, Proceedings of 3rd, Sheraton Towers, Singapore, 2000, pp. 292~296.

    15.H. Noro, S. Ito, M. Kuwamura, and M. Mizutani, “A Study of New Flip Chip Packaging Process for Diversified Bump and Land Combination”, 1998 IEMT/IMC Proceedings, Tokyo, Japan, IEEE, April 1998, pp. 100~105.

    16.K. K. Yu and F. Tung, “Solder Bump Fabrication by Electroplating for Flip-Chip Applications”, 1993 IEEE/CHMT International Electronics Manufacturing Technology Symposium, Santa Clara, CA USA, IEEE, October 1993, pp. 277~281.

    17.Y. T. Chin, C. K. Khor, H. P. Sow, S. J. Ooi, and H. B. Tan, “Breakthrough Ball Attach Technology by Introducing Solder Paste Screen Printing”, 2001 Electronic Components and Technology Conference, 51st, 2001, pp. 198~202.

    18.Y. C. Chan, D. J. Xie, and J. K. L. Lai, “Experimental studies of pore formation in surface mount solder joints”, Materials Science and Engineering B, Vol. 38, 1996, pp. 53~61.

    19.D. J. Xie, Y. C. Chan, and J. K. L. Lai, “An Experimental Approach to Pore-Free Reflow Soldering”, IEEE Transaction on Components, Packaging, and Manufacturing Technology-Part B, Vol. 19, No. 1, February 1996, pp. 148~153.

    20.D. J. Xie, Y. C. Chan, J. K. L. Lai, and I. K. Hui, “Fatigue Life Studies on Defect-Free Solder Joints Fabricated from Modified Reflow Soldering”, IEEE Transaction on Components, Packaging, and Manufacturing Technology-Part B, Vol. 19, No. 3, August 1996, pp. 679~684.

    21.J. Vardaman, Surface Mount Technology Recent Japanese Developments, IEEE Press, New York, 1993, Part 4.

    22.J. H. Lau, Chip on Board Technologies for Multichip Modules, Van Nostrand Reinhold, An International Thomson Publishing Company, New York, 1994, Chapter 5.

    23.D. S. Pattersons, P. Elenius, and J. A. Leal, “Wafer Bumping Technologies-A Comparative Analysis of Solder Deposition Processes and Assembly Considerations”, Advances in Electronic Packaging-1997, Vol. 1, ASME, 1997, pp. 335~339.

    24.J. H. Vincent, and G. Humpston, “Lead-free Solders for Electronic Assembly”, GEC Journal of Research, Vol. 11, No. 2, 1994, pp. 76-89.

    25.H. H. Manko, Solders and Soldering, Second Edition, McGraw-Hill Book Company, New York, 1979, Chapter 2~4.

    26.S. K. Kang, and T. G. Ference, “Nickel-Alloyed Tin-Lead Eutectic Solder for Surface Mount Technology“, Journal of Materials Research, Vol.8, No. 5, 1993, pp. 1033~1040.

    27.M. McCormack, “New Pb-free Solder Alloy with Superior Mechanical Properties“, Apply Physics Letter, Vol. 63, No. 1, 1993, pp. 15~17.

    28.M. Hansen and K. Anderko, Constitution of Binary Alloys, McGraw-Hill, New York, 1958, pp. 1106~1109.

    29.S. H. Huh, K. S. Kim, and K. Suganuma, “Effect of Ag Addition on the Microstructural and Mechanical Properties of Sn-Cu Eutectic Solder”, Material Transition, Vol. 42, No. 5, 2001, pp. 739~744.

    30.J. Glazer, “Microstructure and Mechanical Properties of Pb-free Solder Alloys for Low-Cost Electronic Assembly. A Review”, Journal of Electronic Materials, Vol. 23, No. 8, 1994, pp. 693~700.

    31.C. M. Chuang, T. S. Lui, and L. H. Chen “The Characteristics of Vibration Fracture of Pb-Sn and Lead-Free Sn-Zn Eutectic Solders”, Journal of Electronic Materials, Vol. 30, No. 9, 2001, pp. 1232~1240.

    32.Y. Miyazawa and T. Ariga, “Influences of Aging Treatment on Microstructure and Hardness of Sn-(Ag,Bi,Zn) Eutectic Solder Alloys”, Material Transition, Vol. 42, No. 5, 2001, pp. 776~782.

    33.B. A. Cook, I. E. Anderson, J. L. Harringa, and R. L. Terpstra, “Effect of Heat Treatment on the Electrical Resistivity of Near-Eutectic Sn-Ag-Cu Pb-Free Solder Alloys”, Journal of Electronic Materials, Vol.31, No. 11, 2002, pp. 1190~1194.

    34.邱國展, “電子材料之綠色風潮”, 工業材料170期, 2001, pp. 110~117.

    35.林光隆, “電子構裝覆晶接合技術”, 科儀新知第20卷2期, 1998, pp. 75~79.

    36.M. G. Pecht, L. T. Nguyen, and E. B. Hakim, Plastics-Encapsulated Microelectronics, John Wiley & Sons Inc. , New York, 1995, Chapter 6.

    37.R. J. Hannemann, A. D. Kraus, and M. G. Pecht, Physical Architecture of VLSI Systems, McGraw-Hill, New York, 1989.

    38.馮克林, “封裝元件可靠度加速測試及失效評估”, 工業材料158期, 2000, pp. 90~98.

    39.S. K. Kang, W. K. Choi, M. J. Yim, and D. Y. Shih, “Studies of the Mechanical and Electrical Properties of Lead-Free Solder Joints”, Journal of Electronic Materials, Vol. 31, No. 11, 2002, pp. 1292~1303.

    40.H. P. R. Frederikse, R. J. Fields, and A. Feldman, “Thermal and Electrical Properties of Copper-Tin and Nickel-Tin Intermetallics”, Journal of Apply Physics, Vol. 72, No. 7, 1992, pp. 2879~2882.

    41.J. Y. Park, C. W. Yang, J. S. Ha, C. U. Kim, E. J. Kwon, S. B. Jung, and C. S. Kang, “Investigation of Interfacial Reaction Between Sn-Ag Eutectic Solder and Au/Ni/Cu/Ti Thin Film Metallization”, Journal of Electronic Materials, Vol. 30, No. 9, 2001, pp. 1165~1170.

    42.陳力俊主編, 微電子材料與製程, 中國材料科學學會, 民國八十九年, Chapter 10.

    43.D. S. Liu, and C. Y. Ni, “A Study on the Electrical Resistance of Solder Joint Interconnections”, Microlelctronic Engineering, Vol. 63, 2002, pp. 363~372.

    44.C. Zhang, J. K. Lin, and L. Li, “Thermal Fatigue Properties of Lead-free Solders on Cu and Ni-P Under Bump Metallurgies”, 2001 Electronic Components and Technology Conference, 51st, 2001, pp. 463~470.

    45.D. J. Xie, “A New Experimental Method to Evaluate Creep fatigue Life of Flip-Chip Solder Joints with Underfill, Microelectronics Reliability, Vol. 40, 2000, pp. 1191~1198.

    46.K. D. Kim and D. D. L. Chung, “Effect of Heating on the Electrical Resistivity of Conductive Adhesive and Soldered Joints”, Journal of Electronic Materials, Vol. 31, No. 9, 2002, pp. 933~939.

    47.Z. Tang, and F. G. Shi, “Effect of Preexisting Voids on Electromigration Failure of Flip Chip Solder Bumps”, Microeletronics Journal, Vol. 36, 2001, pp. 605~613.

    48.R. V. Gestel, K. D. Zeeuw, L. V. Gemert, and E. Bagerman, “Comparison of Delamination Effects between Temperature Cycling Test and Highly Accelerated Stress Test in Plastic Packaged Devices”, Reliability Physics Symposium 30th Annual Proceedings, International, 1992, pp. 177~181.

    49.黃家緯, 析鍍條件對銲錫隆點底層金屬無電鍍鎳之成長與擴散障礙行為之影響, 國立成功大學碩士論文, 民國八十九年, pp. 19~36.

    50.鍾明錦, 以錫膏印製Ta/CuTa/Cu/Ni/Au/Solder銲錫隆點及其可靠度之研究, 國立成功大學碩士論文, 民國九十年, pp. 66~84.

    51.J. W. Nah, and K. W. Paik, “Investigation of Flip Chip Under Bump Metallization Systems of Cu Pads”, IEEE Transactions on Components and Packaging Technologies, Vol. 25, No. 1, 2000, pp. 32~37.

    52.J. W. Jang, P. G. Kim, and K. N. Tu, “Crystallization of Electroless Ni-P Under Bump Metallization Induced by Solder Reaction”, Proceedings of International Symposium on Advanced Packaging Materials, Braselton Georgia, 1999, pp. 252~255.

    53.陳俊仁, 以無電鍍鎳銅磷合金做為覆晶接合銲錫隆點底層金屬之研究, 國立成功大學博士論文, 民國九十年, pp. 90~105.

    54.C. E. Ho, Y. M. Chen, and C. R. Kao, “Reaction Kinetics of Solder-Balls with Pads in BGA Packages during Reflow Soldering”, Journal of Electronic Materials, Vol. 28, No. 11, 1999, pp. 1231~1237.

    55.C. E. Ho, R. Zheng, G. L. Luo, A. H. Lin, and C. R. Kao, “Formation and Resettlement of (AuxNi1-X)Sn4 in Solder Joints of Ball-Grid-Array Packages with the Au/Ni Surface Finish, Journal of Electronic Materials, Vol. 29, No. 10, 2000, pp. 1175~1181.

    56.C. E. Ho, W. T. Chen, and C. R. Kao, “Interactions between Solder and Metallization during Long-Term Aging of Advanced Microelectronic Packages, Journal of Electronic Materials, Vol. 30, No. 4, 2001, pp. 379~385.

    57.K. Zeng, and K. N. Tu, “Six Cases of Reliability Study of Pb-free Solder Joints in Electronic Packaging Technology”, Materials Science and Engineering Reports:A Review Journal, Vol. 38, 2002, pp. 55~105.

    58.H. G. Song, J. P. Ahn, A. M. Minor, and J. W. Morris, “Au-Ni-Sn Intermetallic Phase Relationships in Eutectic Pb-Sn Solder Formed on Ni/Au Metallization”, Journalof Electronic Materials, Vol. 30, No. 4, 2001, pp. 409~414.

    59.J. Cai, S. Law, A. Teng, and P. C. H. Chan, ”Influence of Pad Shape and Solder Microstructure on Shear Force of Low Cost Flip Chip Bumps”, 2000 International Symposium on Electronic Materials &Packaging, Braselton, USA, September, 2000, pp. 91~98.

    60.侯振祺, Si/Ta/TaCu/Cu/Ni-P/Sn-Pb銲錫隆點之製作與可靠度研究, 國立成功大學碩士論文, 民國九十年, pp. 69~97.

    61.J. H. Westbrook, and R. L. Fleischer, Magnetic, electrical and optical properties and applications of intermetallic compounds, JOHN WILEY & SONS, LTD, England, 2000, Chapter 2.

    62.J. H. Constable and C. Lizzul, “An Investigation of Solder Joint Fatigue Using Electrical Resistance Spectroscopy”, IEEE Transaction on Components, Packaging, and Manufacturing Technology-Part A, Vol. 18, No. 1, March 1995, pp. 142~152.

    63.Z. Liji, W. Li, X. Xiaoming, and W. Kempe, “An Investigation on Thermal Reliability of Underfilled PBGA Solder Joints”, IEEE Transaction on Electronics Packaging Manufaction, Vol. 25, No. 4, October 2002, pp. 284~288.

    64.K. N. Chiang, Z. N. Liu, and C. T. Peng, “Parametric Reliability Analysis of No-Underfill Flip Chip Package”, IEEE Transactions on components and packaging technologies, Vol. 24, No. 4, December 2001, pp. 635~640.

    65.M. O. Alam, Y. C. Chan, and K. C. Hung, “Reliability study of the electroless Ni-P layer against solder alloy”, Microelectronics Reliability, Vol. 42, No. 7, July 2002, pp. 1065~1073.

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