簡易檢索 / 詳目顯示

研究生: 黃子欣
Huang, Tze-Sing
論文名稱: 低複雜度MPEG-4 simple profile VLSI 實作
VLSI implementation of Low complexity MPEG-4 simple profile video encoder
指導教授: 蘇文鈺
Su, Wen-Yu
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2004
畢業學年度: 92
語文別: 中文
論文頁數: 95
中文關鍵詞: 影像壓縮低複雜度
外文關鍵詞: VLSI, MPEG-4
相關次數: 點閱:69下載:2
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  •   MPEG-4為廣為人之的影像壓縮技術,而在表現出的壓縮效率也讓人滿意,近年來,更是已經有不少相關產品問世。不過MPEG-4壓縮技術也需要的大量計算量,以及需要強而有力的CPU來控制各個模組的運作,所以目前市面上的產品成本一值高居不下。

      在這篇論文中,我們將實作動態預測(Motion Estimation, ME)、離散餘弦轉換(Discrete Cosine Transform, DCT)、量化器(Quantization, Q)、反量化器(Dequantization, DQ)、反轉離散餘弦轉換(Inverse Discrete Cosine Transform, IDCT)、動態補償(Motion Compensation, MC)、直流交流預測器(AC/DC prediction, AC/DC)以及可變長度編碼器(Variable Length Code, VLC),並且我們提出管線化MPEG-4硬體壓縮架構,以及使用低複雜度CPU來控制壓縮流程的方式,來達成高速度的壓縮流程。

      MPEG-4 is an emerging multimedia codec standard, and the encoding performance is satisfactory. For usual, implementation MPEG-4 video compression engine requires huge computation and a powerful CPU to control the computation of modules. Therefore, the MPEG-4 products on the market are always high-priced.

      In this thesis, we implement function unit of Motion Estimation, Discrete Cosine Transform, Quantization, Deqauantization, Inverse Discrete Cosine Transform, Motion Compensation, AC/DC prediction and Variable Length Code. Furthermore we will provide a complete architecture design of MPEG-4 hardware encoder and use a low complexity CPU to control the encoding flow to achieve high-speed compression.

    第一章.緒論 1 1.1.MPEG-4硬體設計簡介 1 1.2.研究動機 2 第二章MPEG-4硬體系統架構 6 2.1.管線化MPEG-4硬體系統架構 6 2.2.管線化MPEG-4影像輸入概述 11 2.3.管線化MPEG-4影像輸入硬體需求 18 第三章 動態估測(Motion Estimation) 19 3.1.動態估測概述 19 3.2.動態估測硬體需求 31 第四章 離散餘弦轉換(Discrete Cosine Transform)、量化器(Quantization)、反量化器(Inverse Quantization)以及反轉離散餘弦轉換(Inverse Discrete Cosine Transform)概述 4.1.離散餘弦轉換概述 32 4.2.量化器概述 34 4.3.反量化器概述 36 4.4.反轉離散餘弦轉換概述 37 4.5.離散餘弦轉換硬體實作概述 38 4.5.1.Y frame離散餘弦轉換硬體實作概述 38 4.5.2.Y frame離散餘弦轉換實作硬體需求 42 4.5.3.UV frame離散餘弦轉換硬體實作概述 42 4.5.4.UV frame離散餘弦轉換實作硬體需求 44 4.6.反轉離散餘弦轉換硬體實作概述 46 4.6.1.Y frame反轉離散餘弦轉換硬體實作概述 46 4.6.2.Y frame反轉離散餘弦轉換實作硬體需求 49 4.6.3.UV frame反轉離散餘弦轉換硬體實作概述 50 4.6.4.UV frame反轉離散餘弦轉換實作硬體需求 50 第五章 AC/DC估測概述 52 5.1.AC/DC估測硬體實作概述 54 5.2.AC/DC估測實作硬體需求 59 第六章 可變長度編碼器概述 60 6.1.可變長度編碼器硬體實作概述 61 6.2.可變長度編碼器輸入輸出概述 71 6.3.可變長度編碼器硬體實作概述 74 第七章MEPG4 硬體實作總述 78 7.1.MPEG4硬體實作控制暫存器 78 7.2.MPEG4硬體回傳資料格式 82 7.3.MPEG4硬體實作整體需求 85 第八章 結論及未來展望 89 附錄A控制碼 91 參考文獻 93

    [1] Eripinh Li, Jens-Rainer Ohm, Mihaela van der Schaar, Hong Jiang, Shipeng Li, “ISO/IEC HTC1/SC29/WG11 N3908 MPEG-4 Video Verification Model version 18.0”, January 2001/Pisa

    [2] TMS320DM270 Digital Media Processor STREAMING MEDIA : TMS320DM270 DIGITAL MEDIA PROCESSOR TMS320DM270 Processor in Texas Instruments

    [3] Li-Hsun Chen; Wei-Lung Liu; Chen, O.T.-C.;Ruey-Liang Ma;”A reconfigurable digital signal processor architecture for high-efficiency MPEG-4 video enoding.”Multimedia and Expo, 2002. ICME ’02. Proceedings. 2002 IEEE International Conference on, Vol.2 pp.26-29 Aug.2002.

    [4] T.Koga, K.Iinuma, A.Hirano, Y. Iijima, and T. Ishiguro, “Motion Compensated Interframe Coding for Video Conferencing,” in Proc.Nat.Telcommun.Conf.,New Orleans,LA,Nov,1981,pp.5.3.1~5.3.5

    [5] Avanindra Madisetti and Alan N.Willson, Jr, Fellow, IEEE, “A 100 MHz 2-D 8x8 DCT/IDCT Processor for HDTV Application”

    [6] W.Chen, Smith C., Fralick S., ”A Fast Computational Algorithm for the Discrete Cosin Transform,” IEEE Trans. Commun. , Vol. COM-25, pp1004-1009, Sept.1997

    [7] Kibum suh, Seongmo Park, Seongmin Kim, Bontae Kuo, Igkyun Kim, Kyungsoo Kim, “An efficiet architecture of DCTQ module in MPEG-4 Video codec.” IEEE international Symopsium on, Vol 1, 26-29 May 2002

    [8] Inter MCS®51 Microcontroller Family User’s Manued Order Number:272383-002 Feb,1994.

    [9] Zahariadis, T. and Kalivas, D., “Fast algorthims for the estimation of block motion vector,” IEEE Electr., Cir., and Syst. 1996. ICECS ’96., Proc. Of the Third IEEE Int. Conf on, Vol.2 pp.716-719, Oct. 1996

    [10] Weiping Li, Fellow, IEEE “Overview of Fine Granularity Scalability in MPEG-4 Video Standard.” Circuits and Systems for Video Techinology, IEEE Trans on Vol. 11, NO 3, March 2001.

    [11] Mihaela van der Schaar, Member, IEEE and Hayder Radha, Member IEEE.”A Hybrid Temporal-SNR Fine-Granular Scalability for Internet Video.” Circuits and Systems for Video Techinology, IEEE Trans on Vol.11 No.3, March 2001.

    [12] Sikora, T. “The MPEG-4 Video standard verification model” Circuits and Systems for Video Techinology, IEEE Trans on, Vol.7 Issue 1, Feb. 1997.

    下載圖示 校內:2014-08-23公開
    校外:2014-08-23公開
    QR CODE