隨著今時今日的科技高速的發展，FPGA以其強大的可編程能力和高性價比，已經可以廣泛地應用在日常生活中的各個方面。其半客制化的特性讓設計者可以依照自己的需求任意更動內部的電路設計，讓FPGA在設計的彈性和簡易程度上勝於ASIC。
本論文是以研究MIPS指令集架構作為初始點，在FPGA的平台上設計一個具有五級流水線，與MIPS指令集架構兼容的32位元RISC微處理器，該處理器採用哈佛架構、數據提前單元與延遲槽指令來解決流水線架構內會產生的數據相依問題。並且額外設計一4路組映射之快取，採用LRU演算法設計，是現今絕大部分快取所使用的演算法，並連結一內部為先進先出(FIFO)構造之載入緩存區，而後再透過Wishbone匯流排與主記憶體RAM做溝通，形成一個完整的電路架構。
最後，本文對設計的微處理器做出驗證，透過Vivado對其進行一個全面的仿真驗證，確保其在各指令功能皆能夠正確運行。而最終結果也證實本論文所設計之RTL級代碼是正確可運行的。

With the rapid development of technology today, The FPGA can be widely used in all aspects of daily life with its powerful programmability and cost-effectiveness, and with the flexibility of FPGA design, we plan to design a RISC microprocessor.
In this paper, we focus on the 32-bit MIPS microprocessor architecture. On the basis of microprocessor core design, the ways of the Harvard architecture, the data forward and the delay slot instruction are used to solve the structure hazards, the data hazards and the control hazards of the pipeline, and we will design a 4 set associative mapping cache to shorten the effective memory access time by using least recently used (LRU) algorithm. connected to a store buffer that is internally FIFO structure, and then they communicate with the main memory RAM through the Wishbone bus to form a complete circuit architecture.
Finally, this paper verifies the designed microprocessor and performs a comprehensive simulation verification through Vivado to ensure that it can operate correctly in each command function. The verification results show that the microprocessor can correctly complete the operation of the instruction.

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