隨著CMOS技術演進，利用應變矽鍺提升P型金氧半場效電晶體元件特性已成為重要的應變工程技術。應變工程使通道內產生壓縮應變力借以增加載子遷移率和驅動電流。然而應力工程的應用不可避免地會遭遇一些問題，例如：應力會受幾何佈局(Layout)及氧化層定義區(LOD)大小的影響，同時亦會產生像是：應力引致缺陷密度、偏壓溫度不穩定性、和熱載流子效應等可靠度相關議題。如何找尋方法去得到通道內之最大應變力是目前主要之課題，而本論文在元件特性和可靠度分析上，觀察到許多從未發表之現象，讓吾人對P型金氧半場效電晶體矽鍺源/汲極應變力之研究有更深一層地了解。
應力會受元件幾何結構、材料、及製程流程各項參數的影響。吾人利用量測數據和模擬結果，針對應變矽鍺源/汲製程之佈局依賴性、應力引致缺陷、矽鍺及淺塹渠絕緣引致應變釋放、和熱載流子現象等各項效應詳細研究，並提出改善元件特性和可靠度的最佳方案。
首先，吾人發現矽鍺源/汲極和淺塹渠絕緣所產生的機械應變力，關係著元件特性及氧化層定義區效應(LOD Effect)的變化。同時，也觀察到模擬閘極(Dummy poly)對矽鍺元件來說扮演一個重要的角色，但對傳統無矽鍺元件卻沒有影響。
其次， 矽鍺源/汲極引致缺陷對未來的元件技術及電路設計上來說，是一個很嚴竣的挑戰。實驗及模擬結果顯示，矽鍺源/汲極應變製程雖可獲得顯著的壓縮應變力，但也會在閘極氧化層及源/汲極延展交界處產生大量的受體態位缺陷，因而導致漏電流的發生。此外，因元件尺寸、通道及淺塹渠絕緣間距離持續縮小的關係，機械應變力受影響愈來愈嚴重。且缺陷密度因為壓縮應變力受到邊界淺塹渠(edge-STI)侷限的關係，隨著元件寬度的縮小，跟著減少。這一點正與非矽鍺傳統製程的特性相反。
另外在可靠度方面，吾人發現熱載流子壓力效應(HCS)加速應變矽鍺源/汲極元件退化的主要機制不同於傳統無矽鍺元件。此外，熱載流子壓力效應因產生大量界面缺陷態位造成閘極氧化層劣化的原因亦被發現：一是因矽和矽鍺晶格錯位所產生之壓縮機械應變力，二是因熱載流子壓力所引發的高電場效應。
最後，深入探討閃光燈熱退火(FLA)對45奈米矽鍺源/汲極P型金氧半場效電晶體p-n界面漏電流之影響。有無快速閃光熱退火的製程會引起不同的界面漏電流。吾人依照活化能的計算結果，分析漏電流機制，並提出模型來証明經過快速閃光燈熱退火製程後，矽鍺源/汲極應變力引致缺陷的現象。

For the advanced CMOS technology, the use of the strained SiGe in PMOSFET S/D regions is one of the most important strain engineering technologies to enhance device performances. The resulting compressive stress in the channel increases the carrier mobility and hence the drive current. However, strain engineering would inevitably raise concerns such as: strain induced defect density, geometry, LOD effects, and reliability problems (e.g. NBTI, PBTI and Hot Carrier effects etc.). The primary research topic is to explore pathways to maximize the desired strain in the device channel. This thesis studies some unprecedented phenomena for better understanding of SiGe S/D strain effect in PMOS device performance and reliability issue.
The stress is a function of various parameters such as geometry of the structure, materials, process flow, and etc. A set of variables such as stress layout dependence, stress relaxation due to SiGe S/D and STI, stress-induced defects, and hot carrier effect for SiGe S/D process have been addressed and understood with the help of silicon data and simulation results. As a result, compromises between the improvement of device performance and device reliability are proposed.
Firstly, in this thesis, we investigate that the mechanical stress resulted from the strained SiGe S/D and STI significantly impacts device performance and length of thin oxide definition area (LOD) effect. The results suggest that the dummy gate plays a significant role in the SiGe sample, but does not induce LOD effect in the non-SiGe device.
Secondly, defects induced from the SiGe S/D strain become a crucial challenge for the future device technology and circuit design. The measurements and simulation results show that the embedded SiGe S/D strain process creates a significant compressive strain, and generates a large number of acceptor-like states at the interface of gate oxide and S/D extension regions to result in the leakage current. Furthermore, the mechanical stress issue will become more and more serious for the continuous shrinking active area and the shorter distance between the channel and the STI edge. The compressive stress is limited by edge-STI, thus decreasing defect density in narrower width, as opposed to the conventional non-SiGe devices.
Thirdly, we study the reliability issues and find that the dominant mechanism of HCS degradation in strained SiGe S/D devices is different from that in non-SiGe S/D devices. In addition, some sources to deteriorate the gate dielectric for Nit generation are also found; one is the compressively mechanical stress resulted from the lattice mismatch between Si and SiGe; and the other is the high electric field resulted from the HCS.
Finally, we deeply investigate the effect of flash lamp annealing (FLA) on the S/D p-n junction leakages of a 45 nm PMOSFET with strained SiGe S/D. The SiGe S/D PMOSFETs with and without FLA have different behaviors in junction leakage currents. Based on activation energy (Ea) measurements, we analyze the leakage mechanisms in detail, and give models to explain the phenomenon of SiGe S/D induced defects after FLA processing.

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