NAND型快閃記憶體元件擁有高儲存密度、高存取速度、與低單元成本，適合使用在大量儲存裝置，目前已廣泛地應用到3C行動產品當中。本論文的主要研究目的在於探討NAND Flash周邊電路元件的可靠度與元件特性。由於在NAND Flash記憶體單元進行資料寫入與抹除時需要供給高電壓，記憶體單元的周邊元件：字元線驅動(Word line driver)電路便需要將上級電路的高電壓傳送至記憶體單元。這時正在傳送訊號的周邊元件即受到對於基板而言，大的汲極偏壓(VDS)與源極偏壓(VSB)。本論文將探討控制傳送高電壓訊號開關的周邊元件，在傳遞訊號時伴隨著高電壓訊號跟基板偏壓的過程中熱載子效應對此周邊元件的可靠度影響。
　　周邊元件在切換開關的過程中，會經過幾種特定偏壓情形，像是高汲極偏壓與高基板偏壓的情況，或是產生高基板電流的狀況，對於這些產生熱載子效應與碰撞游離的情況來進行熱載子加壓實驗，得知退化機制、可靠度、與元件的生命週期，並藉由TCAD模擬來證實實驗結果。結果指出高汲極偏壓會導致熱載子效應，造成線性區汲極電流(IDlin)明顯退化；高基板偏壓會導致元件內部之垂直電場增加，導致通道下方發生第二次碰撞游離，注入的載子使得閘極對通道的控制能力降低，並造成元件的臨界電壓(VTH)偏移。
　　接著探討汲極輕摻雜(Lightly Doped Drain)的不同長度對元件之可靠度造成的影響，我們將不同輕摻雜長度範圍的元件進行加壓實驗，從實驗結果可以得知不同長度的輕摻雜之元件退化的機制都相同，並且如同預期中特性類似短通道元件，輕摻雜區越短耐壓程度越差，另外定義出元件的生命週期(lifetime)，探討不同尺寸對生命週期的影響，也證實了通道兩邊有著不同長度，但總長度相同的輕摻雜區，將該不對稱元件反過來接，可得到基本電性相同，而耐壓程度不同的結果。

　　Recent years, NAND flash memory device which has been widely applied to 3C mobile products is suitable for mass storage devices because of high storage density, high access speed, and low unit cost. The main purpose of this thesis is about reliability and performance of peripheral devices in NAND flash memory. Since NAND flash memory cell needs high voltage for program - erase cycle, the peripheral device of cell, word line driver circuit, has to transmit high voltage to memory cell from superior circuit. The device transmitting signals receives a large VDS and VSB for substrate. This thesis investigated about reliability of high voltage peripheral devices affected by hot carrier effect with high voltage signals and body bias during transmitting condition.
　　The peripheral device would pass through some specific bias in the process of switching, such as high drain bias and high substrate bias, or the generating large substrate current condition. We did hot carrier stress experiments in these situations and found out degradation mechanisms, reliability, and lifetime of device. These results were verified by TCAD simulations. Results indicated that a high drain bias led to hot carrier effect resulting in significant degradation of drain current in linear region(IDlin), and a high substrate bias led to second impact ionization under channel resulting in a threshold voltage(VTH) shift owing to increased vertical electric field inside device.
　　The other part of this thesis, we research the different LDD(Lightly Doped Drain) length of for the impact of the reliability of devices. After stressing different LDD length devices, the experimental results conformed to expectation that the degradation mechanisms were the same, and characteristics resembled in short channel devices, the shorter the LDD length, the poor the immunity to stress. We also defined the lifetime of devices to investigate impact on lifetime in different dimension. The last part gave evidence for result that two devices with the same total LDD length but different length in source and drain region have the same characteristics but obtain different degradation after stress.

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