近年來電子產品尺寸的縮小以及功能性的增加，使得電子產品晶片所需要的接腳數增加，覆晶封裝技術可以將接腳排列於晶片的平面上，增加接腳數。覆晶封裝僅將隆點佈植於晶片上直接連接於基板上，而封裝過程溫度的變化造成隆點與基板接觸的接合點因熱膨脹係數的不同，在隆點上產生應力造成接合處剝落毀損。為了降低接點損壞，覆晶封裝技術在晶片與基材之間的空隙充填入底部封膠，封膠充填的動力為毛細作用所造成的壓力差，使得充填所需的時間較長且容易造成有封包現象的不良產品。在本研究中，我們以避免封包現象以及減小充填時間提高充填效率為目標。
在本實驗中，我們探討錫鉛隆點間距的不同，對封膠充填行為所造成的影響。以數值模擬的方式，模擬在邊際效應的條件下，錫鉛隆點排列的不同，造成充填流場的變化，且以最佳化的方法，搜尋充填所需要時間最小值以及對應的錫鉛隆點排列方式。

In recent years, the chip of electronic product needs more I/O ports because of the smaller size and more integration. In order to increase the3 number of I/O ports, flip chip technology arranges I/O ports on the chip surface. Solder bumps on the chip are used to connect the chip and substrate. Due to the mismatch of the coefficients of thermal expansion (CTE) at the contact point between the bump and substrate, thermal stress may build up to cause damage as subjected to temperature variations. In order to reduce the thermal stresses at the contact point, the underfill encapsulation is introduced to the gap between the chip and substrate by the capillary flow. The underfill encapsulation process suffers from the problems of long filling time and formation of voids in the case of fine pitch bump arrangement. In the study, we try to study the arrangement of bumps to reduce the filling times and avoid void formation in the underfill process.
In the study, we confer the influence of underfill encapsulation process with different bump pitches. We use numerical simulation method to simulation the underfill flow for different bump pitches with the edge effect. An optimization method is also used to derive the bump arrangement to minimize the filling time.

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