本論文針對不同條件的水表面處理與氨電漿處理，探討對高介電係數介電層 (二氧化鉿)與矽鍺介面的影響。從眾多文獻的比較中，可以發現大部分矽鍺電容的介電層都大於5奈米，隨著介電層厚度減少，矽鍺介面的品質對於電性表現的影響漸漸增加。而本論文為了追求更小的EOT，介電層厚度約3奈米，若要有良好的電性表現，對於矽鍺介面的品質要求更高，因此我在製程中加入氨電漿處理鈍化矽鍺表面。
氨電漿處理可以在氧化層表面形成一層阻擋層，防止鍺在後續製程擴散進二氧化鉿介電層，同時抑制水氣擴散到矽鍺表面。同時，在高溫的氨電漿處理下，由於反應速率提升，所形成的阻擋層抑制能力較高；另一方面，水表面處理在高溫下因為氧化鍺的擴散，易產生較多介面缺陷。根據實驗結果，在250°C水表面處理與氨電漿的條件下，電容在沉積後退火(500°C，30秒)後，電性上顯示有較小的遲滯現象(約189.67 mV)與等效電容厚度(1.63奈米)，且閘極漏電流在閘極電壓為-1 V時，約為1.75×10-5 A/cm2，最後成功應用在鰭式電晶體中。

In this thesis, we use different conditions of H2O treatment and NH3 plasma treatment to investigate the influence on high-k dielectrics/SiGe interface. In-situ NH3 plasma nitridation has been used to passivate the HfO2/SiGe interfaces and form a diffusion barrier. It is noticed that the diffusion barrier may suppress not only diffusion of GeOx from the semiconductor surface into the gate oxide, but H2O diffuses to the SiGe surface. On the other hand, H2O treatment performed at high temperatures easily create more defects due to the outdiffusion of GeO. According to our experimental results, the nitrided TiN/HfO2/SiGe/Si MOSCAP shows a small C-V hysteresis loop of ~189.67 mV and low capacitance equivalent thickness (CET) of 1.63 nm, and leakage current density (Jg) of ~1.75×10-5 A/cm2 at a gate bias of Vg = -1.0 V. Then, performing on FinFETs.

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