| 研究生: |
郭餘之 Kuo, Yu-Chih |
|---|---|
| 論文名稱: |
先進電子封裝熱網路模型高效率萃取方法之研究 Research on High-Efficiency Extraction Method for Thermal Network Model of Advanced Electronic Packages |
| 指導教授: |
楊天祥
Yang, Tian-Shiang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 機械工程學系 Department of Mechanical Engineering |
| 論文出版年: | 2023 |
| 畢業學年度: | 111 |
| 語文別: | 中文 |
| 論文頁數: | 103 |
| 中文關鍵詞: | 電子封裝 、熱傳模擬 、序列最小平方規劃法 、基因演算法 、熱網路模型 |
| 外文關鍵詞: | electronic packaging, thermal analysis, sequential least square programming, genetic algorithm, thermal network model |
| 相關次數: | 點閱:30 下載:0 |
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本研究討論了電子散熱和溫度模擬的相關性,以及如何使用熱網路模型來有效解決系統級數值模擬中的問題。首先,準確的數值模擬對於電子系統散熱設計至關重要。然而,由於電子系統之尺寸遠大於電子封裝體之微小特徵尺度,解析微小特徵的影響將導致網格數量爆增。為了解決此問題,可以使用電子封裝體的熱網路模型將封裝體簡化成僅有數個節點,以有效減少網格數量。
接著,研究通過數值模擬計算兩種電子封裝模型:單晶片及並列式雙晶片覆晶晶片尺寸級封裝體在各式邊界條件組合下之熱傳表現,並根據電子封裝體的結構設置熱網路模型之節點。為了確保熱網路模型的準確性,利用根據熱網路模型與實際模型的熱傳表現差值定義之目標函數和最佳化方法,將熱網路模型的熱傳表現與實際模型一致化。研究比較了序列最小平方規劃法和基因演算法的效果,並討論了最佳化參數和初始猜值對結果的影響。
結果顯示,序列最小平方規劃法結合在關鍵路徑使用等效熱阻計算求得初始猜值的方法,可比基因演算法更快速有效的萃取熱網路模型。此外,本研究提出一個進一步提升熱網路模型準確性的方法,通過細分較大誤差邊界條件下之主要熱傳等溫面後重新進行訓練,此新求得的熱網路模型,其溫度誤差會顯著降低並且與實際模型相符。
總結而言,本研究探討了使用熱網路模型進行電子系統熱傳模擬的方法,並提出一個有效提高熱網路模型的準確性與其訓練效率的演算法,大幅地降低訓練所需之時間成本。此演算法對於單晶片或多晶片封裝皆一體適用。這些結果對於改善電子系統的散熱效能和設計過程具有重要意義。
In order to reduce the number of grids in numerical computations that involve multiple length scales, here we propose to reduce an electronic package to a small number of surface and junction temperature nodes that are related by a network model. To that end, first we calculate the temperature distributions in a continuum electronic package (referred to as the detailed model hereafter) subjected to the various boundary conditions (BCs) set by JEDEC. Then a corresponding network model is constructed, and the junction temperatures are calculated for the same heat dissipation power as that for the detailed model, under the same JEDEC BCs. An objective function, which combines the weighted discrepancies of junction temperature and surface heat fluxes between the numerical results from the detailed and that from network models, is defined and minimized by tuning (or, in more fashionable terms, “training”) the tunable thermal resistance parameters of the network model. The strategy outlined above is applied to flip chip chip-scale package (FCCSP) that contains a single chip or dual chips. The minimization of the objective function is achieved using both techniques of the sequential least square programming (SLSQP) and genetic algorithm (GA). For SLSQP, it is found that using the initial estimates of the thermal resistance parameters in the network model obtained through 1-D simplification of the package can substantially help guiding the objective function to converge to its “true” minimum (as opposed to a certain local minimum). And the “optimized” network model can predict the junction temperature for all JEDEC BCs within error. Meanwhile, GA without using the aforementioned proper 1-D initial estimates of the thermal resistance parameters does not significantly improve the training results, but consumes substantially more computing time. In this study, we also demonstrate that the network model can be further improved by systematically increasing its spatial resolution based upon the various errors observed in primary attempts.
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