在此論文中，我們製做多晶矽薄膜電晶體與多晶矽穿隧式場效電晶體，並且在室溫下施加正偏壓應力研究其可靠度行為，對於多晶矽薄膜電晶體，常態量測中因為其一載子傳輸機制是電場調變擴散與遷移，其二擁有較大的傳導截面積所以擁有較高的開啟電流達3.08x10-4，在分別施加閘極正偏壓應力15V、20V、25V後汲極電流曲線開始出現劣化，經過1000秒的應力後，次臨界擺幅變量為0.34V/dec(正偏壓應力閘極20V)到 0.65V/dec(正偏壓應力閘極25V)，轉導的最大值也下降42μS (正偏壓應力閘極20V) 到71μS(正偏壓應力閘極25V)，對於多晶矽穿隧式場效電晶體，常態量測中擁有比較低的次臨界擺幅歸咎於較低的源極參雜與陷阱輔助穿隧效應，意外發現施加閘極正偏壓應力後改善了次臨界擺幅與臨界電壓，但轉導的最大值依舊下降，我們推測兩個原因: 第一，這些應力產生的陷阱態已被電子填補，總陷阱密度下降而提升次臨界擺幅，但有研究顯示其填補只是暫態行為而且薄膜電晶體的次臨界擺幅並未改善，第二，應力讓原有的陷阱態產生同一能階的陷阱態，因為陷阱輔助穿隧效應正是穿隧式電晶體在次臨界區的載子傳輸機制，所以陷阱態的能階分布對其特性影響極大，如果應力造成陷阱態能階分布改變使其產生同一能階的陷阱態將可以大大降低陷阱輔助穿隧電流並提升次臨界擺幅。

In this study, we fabricated and demonstrated poly-Si TFTs and poly-Si TFET with positive bias reliability research in low temperature. For TFT device, it demonstrates higher on current up to 3.08x10-4 A due to carrier transport mechanism of electric field drift and larger effective conduction area. Id-Vg curve starts to split up with different subthreshold swing after gate voltage stress. The SS shift after 1000sec stress from 0.34V/dec to 0.65V/dec and maximum of transconductance variation Δgmmax from 42μS to 71μS for gate stress 15V and 25 V respectively. For TFET device, poor S.S. degradation is due to the low source doping concentration and the trap assisted tunneling (TAT). Positive Bias Stress only improve SS and Vth of TFET without gm. We implied two possibilities. Firstly, stress generated traps be recovered and compensated by electrons might be the reason. However, as studies shows that the recovery and compensation of traps from carrier are only temporary condition. Secondly, stress create traps with the same energy level to reduce TAT current. Since TAT is dominant TFET degradation of subthreshold region, density of traps and trap energy are important for SS behavior. If stress change traps energy distribution that produces the same traps level, TAT current could be reduce by limiting tunneling direction then suppress SS deterioration.

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