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研究生: 葉品蓁
Yeh, Pin-Chen
論文名稱: 具頻率校正之注入鎖定喚醒接收機及抵抗振盪器對電源雜訊影響技術
An Injection-Locking Based Wake-Up Receiver with Frequency Calibration and Supply Noise Insensitive Techniques
指導教授: 鄭光偉
Cheng, Kuang-Wei
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2024
畢業學年度: 112
語文別: 英文
論文頁數: 115
中文關鍵詞: 物聯網喚醒接收機注入鎖定振盪器頻率漂移連續逼近內差法抵抗電源雜訊鎖相迴路電流抵消技術
外文關鍵詞: Internet-of-things (IoT), injection-locking, oscillator, wake-up receiver, frequency drifting, Successive Approximation Algorithm, supply noise insensitive, phase-locked-loop, noise cancelling
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  • 這篇論文介紹了一種針對物聯網應用中無線感測器網絡中的高靈敏度喚醒接收器(WuRx)設計的頻率校準方法。 伴隨這種校準方法的是一種適用於振盪器的抗供電雜訊技術。振盪器頻率漂移的問題,歸因於工藝、電壓和溫度(PVT)變化,可能會顯著影響無線網絡中WuRx的靈敏度。此外,它可能會影響有線傳輸中的相位雜訊(PN)和抖動性能。為了解決這些挑戰,本文提出了一種採用適用於多模式WuRx的逐次逼近寄存器(SAR)算法的頻率校準技術。這種10位SAR搜索算法可以在啟動信號接收之前對頻率進行精確校準。
    同時,引入了供應噪聲電流抵消(SNCC)技術作為傳統低壓差(LDO)穩壓器的替代品,為電流控制振盪器(CCO)提供了一個不受供應噪聲影響的偏置電路。提出的SNCC-CCO在1MHz至10MHz範圍內顯示出顯著的功率供應噪聲減少,有效地減輕了電壓變化。同時,該提出的技術在相位鎖定環(PLL)中應用時可以實現低抖動性能。基於注入鎖定的WuRx設計,配合頻率校準,採用TSMC 180nm CMOS混合信號工藝實現,工作電壓為1V。此外,供應噪聲不敏感振盪器的設計也是在TSMC 40nm CMOS工藝中實現的,供應電壓同樣為1V。

    The thesis presents a frequency calibration method for high-sensitivity Wake-Up Receivers (WuRx) in IoT wireless sensor networks. Alongside, a supply noise insensitive technique for oscillators is introduced. Oscillator frequency drifting, caused by process, voltage, and temperature (PVT) variations, can significantly impact WuRx sensitivity and PN and jitter performance in wired transmissions. To tackle these challenges, the thesis proposes a frequency calibration technique using a 10-bit SAR algorithm for multi-mode WuRx. This SAR algorithm ensures precise frequency calibration before signal reception initiation.
    Simultaneously, the supply noise current canceling (SNCC) technique is introduced as a substitute for traditional Low Drop-Out (LDO) regulators, providing a supply-noise insensitive bias circuit for the current-controlled oscillator (CCO). The proposed SNCC-CCO demonstrates significant reduction in power supply noise within the 1MHz to 10MHz range, effectively mitigating voltage variations. Meanwhile, the proposed technique can achieve low jitter performance when applying it in a phase-locked-loop (PLL).
    The design of the injection-locking-based WuRx with frequency calibration is implemented in the TSMC 180nm CMOS mixed-signal process, operating at a voltage of 1V. Additionally, the design of the supply noise-insensitive oscillator is implemented in the TSMC 40nm CMOS process, with a supply voltage of 1V as well.

    1. Introduction - 1 - 1-1. Motivation - 1 - 1-2. Thesis Overview - 2 - 2. Survey of Existing Research - 3 - 2-1. Low Power Schemes for Wireless Sensor Networks - 3 - 2-1-2. Pseudo-Asynchronous Scheme - 4 - 2-1-3. Pure Asynchronous Scheme - 5 - 2-2. Receiver Architecture - 5 - 2-2-1. Direct Envelope Detection Wake-up Receiver - 6 - 2-2-2. Mixer First Wake-up Receivers - 7 - 2-2-3. Super Regenerative Receivers - 9 - 2-2-4. Injection-Locked Oscillator Based Receivers - 11 - 2-3. Frequency Calibration Technique - 13 - 2-3-1. Background Calibration - 13 - 2-3-2. Pre-Calibration - 14 - 2-4. Supply Noise Compensation Technique - 16 - 2-5. Performance Metrics and Specifications - 19 - 2-5-1. Frequency Calibration WuRx - 19 - 2-5-2. Supply Noise Insensitive CCO - 20 - 3. Multi-Mode Injection-Locking based Wake-up Receiver with Frequency Calibration - 25 - 3-1. Analysis of Multiple Demodulation Scheme - 26 - 3-1-1. Basic operation of Injection-Locked oscillator - 26 - 3-1-2. Multi-Mode Demodulation Scheme - 28 - 3-2. Proposed Frequency Calibration Circuit using Successive-Approximation Algorithm (SAR) - 30 - 3-2-1. Frame Work Analysis - 30 - 3-2-2. Proposed Calibration System and Timing Diagram - 33 - 3-3. Circuit Implementation and Simulations - 35 - 3-3-1. 10b Injection-Locked Oscillator - 35 - 3-3-2. Reference Divider and Synchronize Counter - 41 - 3-3-3. 15-bits Full Adder - 43 - 3-3-4. Successive-Approximation Algorithm - 44 - 3-3-5. Digital Baseband Decoder - 47 - 3-4. Whole Chip Simulation Results - 51 - 3-4-1. Power Consumption - 53 - 3-4-2. Comparison Table - 54 - 3-5. Measurement Result - 55 - 3-5-1. Measurement Setup - 55 - 3-5-2. SPI Configuration - 56 - 3-5-3. ILO and Frequency Calibration Measurement - 57 - 3-5-4. WuRx Sensitivity and Wake-up Test - 60 - 3-6. Conclusions - 63 - 4. Supply Noise Insensitive Current Controlled Oscillator - 65 - 4-1. Supply Noise Current Cancellation Bias Circuit (SNCC) - 66 - 4-1-1. Supply Noise Current Cancellation Concept - 66 - 4-1-2. Noise Analysis - 68 - 4-1-3. Design Considerations - 70 - 4-1-4. Simulation Results - 71 - 4-2. Current Controlled Oscillator Implementation - 76 - 4-2-1. VI-Converter - 76 - 4-2-2. Delay Cells and Buffer - 78 - 4-2-3. Coarse Tune/ Fine Tune DAC - 80 - 4-3. Chip Simulation Results - 82 - 4-4. Measurement Results and Discussion - 85 - 4-4-1. Measurement Setup - 85 - 4-4-2. Measurement Result - 87 - 4-4-3. Performance and Brief Summary - 94 - 4-5. Conclusions and Future Work - 94 - 5. Conclusions and Future Work - 95 - 5-1. Discussion and Future Work - 95 - 5-1-1. ILO-Based WuRx with Frequency Calibration (Chip #1) - 95 - 5-1-2. Supply-Noise-Current-Cancellation-CCO (Chip #2) - 95 - 5-1-3. Summary - 96 - 5-2. Conclusion - 97 - Reference - 99 -

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