本論文研究以原子層沉積技術沉積高介電係數氧化層及其與鍺基板之界面層製備低等效氧化層厚度金氧半電容器與電晶體，為延續摩爾定律與提升元件的特性，需將電晶體不斷地微縮，作為閘極氧化層的二氧化矽亦須不斷地減薄，然而這也同時間提高了閘極漏電流與降低元件可靠度，因此元件的材料與結構必須隨之改變。鍺基板擁有較矽基板較高的載子遷移率，可以致使元件擁有較好的表現，此外，高介電常數材料如氧化鋁、二氧化鉿可代替傳統的二氧化矽作為介電層。事實上鍺基板與高介電常數材料之界面有許多界面缺陷產生，可能造成漏電路徑、通道散射效應導致元件的劣化。為解決此問題，在鍺基板與高界電常數氧化層中加入一界面氧化層並予以氮化，可以鈍化界面陷阱外，還可避免因高溫而析出的氧化鍺擴散至介電層。在傳統上是利用氮電漿或氨電漿來進行氮化製程，但過程中的電漿將會同時轟擊晶片表面，可能降低介面層之品質。因此本研究提出以聯氨作為一種替代方案以進行鈍化製程。
聯氨為一種高活性的化學材料，僅需給予熱能使之熱裂解便能提供氮化處理所需的氮原子，實現無電漿態的鈍化製程。透過原子層沉積技術在鍺基板的表面進行氧化及氮化反應，形成厚度約為10Å氮氧化鍺的界面層，並與氧化鋁、二氧化鉿等高界電常數材料在同一腔體內完成沉積，以減少外界環境污染所造成的影響，最後沉積氮化鈦製成金氧半電容器，並將最佳的電容器條件應用於鰭式電晶體。
最後，我們將採用上述的閘極堆疊條件並應用於鍺基板鰭式電晶體和閘極環繞式電晶體，在P 型鰭式電晶體中，其展示了94.82 mv/dec.的次臨界擺幅，開關電流比為1.2x105。至於 N 型鰭式電晶體中，可觀察到次臨界擺幅為89.28 mv/dec.，開關電流比為2.5x104。閘極環繞式電晶體顯示了次臨界擺幅為80.57 mv/dec.，開關電流比為1.11x106。

In this thesis, we investigate the different high dielectric constant (high-k) materials and interfacial layers fabricated by atomic layer deposition (ALD) technique on Ge metal-oxide-semiconductor capacitors (MOSCAP) along with FinFETs. In order to follow Moore’s law and enhance the devices performance, not only do transistors need to be continuously scaled down, but SiO2, used as gate oxide layer, has to be thinned down. However, higher gate leakage current and lower reliability of devices come right after those benefits. As a result, the materials and structures should be modified with the technology nodes. Germanium has higher carrier mobility than silicon, which contributes to better devices performance. Additionally, high-k materials such like Al2O3 and HfO2 could replace traditional SiO2 as gate oxide layer with lower equivalent oxide thickness (EOT) . According to the advantages mentioned above, germanium and high-k materials seem to be outstanding candidates for conquering those obstacles while scaling. As a matter of fact, numerous defects existing in the interface between germanium and high-k materials probably lead to leakage path and severe channel scattering effect and thus devices degrades. To address this problem, we could apply an interfacial layer with nitrogen treatment on the interface between germanium substrate and high-k dielectrics to passivate interfacial traps and prevent germanium monoxide (GeOx) from diffusing because of high temperature. Traditionally, the nitridation process is completed by N2 plasma or NH3 plasma while the plasma is going to bombard the surface of the substrate, which might decrease the quality of the interfacial layer. Consequently, this research proposes an alternative approach to conduct the passivation process with hydrazine.
Hydrazine, a kind highly active chemical materials, needs only thermal energy to decompose and provides the nitrogen atoms in the plasma-free nitridation treatment. The oxidation and nitridation reaction are applied on the surface of germanium substrate to form a thickness of approximately 10Å germanium oxynitride (GeON) as interfacial layer through ALD. In the meanwhile, the high-k dielectrics, like Al2O3 and HfO2, are deposited in the ALD chamber so as to reduce the influence induced by outside environment. The fabrication of MOS capacitors is completed by TiN deposition, and then the optimized condition will be applied to FinFETs.
Finally, we adopted the high-k gate stacks and apply to Ge FinFET and gate-all-around FET (GAAFET). The electrical characteristics are studied in this thesis. We demonstrated subthreshold swing (S.S.) of 94.82 mv/dec. and Ion/Ioff ratio of 1.2x105 for Ge p-FinFET. As for NFET, the S.S. of 89.28 mv/dec. and Ion/Ioff ratio of 2.5x104 can be observed. Ge n-GAAFET exhibits S.S of 80.57 mv/dec, Ion/Ioff ratio of 1.11x106.

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