隨著人工智慧的快速發展,電腦運算的速度和能耗逐漸受到重視。然而,目前的科技發展仍受限於傳統的馮諾伊曼架構,難以滿足日益增長的計算需求。近年來，人工智慧與機器學習的討論中，類人腦的神經型態運算成為了一個熱門的研究方向。這種計算架構受到生物神經系統的啟發，通過模擬神經元和突觸的行為，實現高效、低功耗的運算。其中，憶阻元件因其獨特的電阻值可變特性，在構建人工神經突觸方面展現出了巨大的潛力。本文將探討如何利用以二硒化鎢WSe2為基底的憶阻元件實現模擬神經突觸的各個現象。

在這個碩士論文中，由於現今憶阻器或憶阻電晶體在幾個原子層厚度的研究十分稀少，因此我們致力於研究原子級厚度的元件，研究探討其在憶阻器和憶阻電晶體這個領域的表現，我們以WSe2為基底，製作了三種不同的結構:

三層WSe2(memtransistor A)、人工堆疊WSe2/1L-WOx/WSe2(memtransistor B)和最上層氧化1L-WOx/WSe2(memtransistor C)為了去完整的了解元件表面和介面捕獲(trapping)的行為以及WOx在元件中扮演的角色和工作機制。使用施加閘極電壓脈衝的方式去模擬前突觸和後突觸的表現，而我們也著重在三層WSe2的相關實驗，成功量測到了雙脈衝增益 (PPF)、成對脈衝抑制 (PPD)、增抑迴圈 (P/D cycle)，藉由這些數據得到了高達821的電導比和低至3.8奈焦耳的能耗；在人工堆疊結構的元件上，我們也量測到脈衝時序依賴可塑性(SDDP) 等的可塑性現象。

這篇碩士論文為原子層厚度的WSe2憶阻元件提供了初步的研究結果，揭示了極少層數WSe2在憶阻器應用中的潛力，為未來高效、低功耗神經型態計算系統的開發奠定了基礎。未來的研究可以進一步改變脈衝量測時的參數，使其產生更低的能耗。

With the rapid development of artificial intelligence, the speed and energy consumption of computing has received much attention. However, current technologies are limited by the traditional von Neumann architecture, making it difficult to meet the growing computational requirements. In recent years, human-brain-like neuromorphic computing has been presented as a possible solution and has become a hot research direction in the discussion of artificial intelligence and machine learning. This computing architecture is inspired by biological neural systems and achieves efficient and low-power computing by simulating the behavior of neurons and synapses. Among neuromorphic computing, memristive devices have shown great potential in constructing artificial neural synapses due to their unique variable resistance characteristics. This thesis will explore how memristive devices based on tungsten diselenide (WSe2) simulate various of neural synaptic plasticities.
There are very few studies on memristors or memtransistors for atomic layer thickness WSe2, therefore in this thesis we aim to fill this gap by devices studying ultrathin devices and exploring their performance in the field of memristors and memtransistors. We used WSe2 as the material and fabricated three different forms of structures: trilayer WSe2 (memtransistor A), artificial stacked WSe2/1L-WOx/WSe2 (memtransistor B), and top-layer oxidized 1L-WOx/WSe2 (memtransistor C) to further understand the surface or interface trapping behavior and the role of WOx in the working mechanism of devices. By applying gate voltage pulses, we simulated the behavior between pre-synapses and post-synapses. We focused on the experiments related to trilayer WSe2 and successfully measured paired-pulse facilitation (PPF), paired-pulse depression (PPD), and potentiation-depression cycles (P/D cycles), achieving a high conductance ratio of up to 821 and low energy consumption of 3.8 nJ. In the devices with artificial stacked structures, we also observed plasticity such as spike-timing-dependent plasticity (STDP).
This master's thesis provides preliminary research results for WSe2 memristive devices with atomic layer thickness, revealing the potential of ultra-thin WSe2 in memristor applications and laying the foundation for the development of future efficient and low-power neuromorphic computing systems. Future research can further optimize the pulse measurement parameters to achieve even lower energy consumption.

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